6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-06 04:31:08 +00:00
Code Issues Projects Releases Wiki Activity

R600: Rewrite an awkward loop in R600MachineScheduler

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-06-06 23:08:32 +00:00
parent 9342b9ccdd
commit 81c5d11c25
1 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/R600/R600OptimizeVectorRegisters.cpp
View File

@ -159,6 +159,19 @@ bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
return true;
}
static
unsigned getReassignedChan(
const std::vector<std::pair<unsigned, unsigned> > &RemapChan,
unsigned Chan) {
for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
if (RemapChan[j].first == Chan) {
return RemapChan[j].second;
break;
}
}
llvm_unreachable("Chan wasn't reassigned");
}
MachineInstr *R600VectorRegMerger::RebuildVector(
RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
const std::vector<std::pair<unsigned, unsigned> > &RemapChan) const {
@ -179,13 +192,8 @@ MachineInstr *R600VectorRegMerger::RebuildVector(
unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
unsigned SubReg = (*It).first;
unsigned Swizzle = (*It).second;
unsigned Chan = 0xDEADBEEF;
for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
if (RemapChan[j].first == Swizzle) {
Chan = RemapChan[j].second;
break;
}
}
unsigned Chan = getReassignedChan(RemapChan, Swizzle);
MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
DstReg)
.addReg(SrcVec)