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When expanding ARM pseudo registers, copy the existing predicate operands

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instead of using default predicates on the expanded instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-09-16 04:25:37 +00:00
parent a8e47b3319
commit 823611bfba
1 changed files with 29 additions and 9 deletions
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38
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -367,12 +367,21 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
if (TableEntry->HasWriteBack) if (TableEntry->HasWriteBack)
MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++));
MIB = AddDefaultPred(MIB);
// For an instruction writing double-spaced subregs, the pseudo instruction // For an instruction writing double-spaced subregs, the pseudo instruction
// has an extra operand that is a use of the super-register. Copy that over // has an extra operand that is a use of the super-register. Record the
// operand index and skip over it.
unsigned SrcOpIdx = 0;
if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
SrcOpIdx = OpIdx++;
// Copy the predicate operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addOperand(MI.getOperand(OpIdx++));
// Copy the super-register source operand used for double-spaced subregs over
// to the new instruction as an implicit operand. // to the new instruction as an implicit operand.
if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) { if (SrcOpIdx != 0) {
MachineOperand MO = MI.getOperand(OpIdx); MachineOperand MO = MI.getOperand(SrcOpIdx);
MO.setImplicit(true); MO.setImplicit(true);
MIB.addOperand(MO); MIB.addOperand(MO);
} }
@ -407,7 +416,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++));
bool SrcIsKill = MI.getOperand(OpIdx).isKill(); bool SrcIsKill = MI.getOperand(OpIdx).isKill();
unsigned SrcReg = MI.getOperand(OpIdx).getReg(); unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
unsigned D0, D1, D2, D3; unsigned D0, D1, D2, D3;
GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
MIB.addReg(D0).addReg(D1); MIB.addReg(D0).addReg(D1);
@ -415,7 +424,11 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
MIB.addReg(D2); MIB.addReg(D2);
if (NumRegs > 3) if (NumRegs > 3)
MIB.addReg(D3); MIB.addReg(D3);
MIB = AddDefaultPred(MIB);
// Copy the predicate operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addOperand(MI.getOperand(OpIdx++));
if (SrcIsKill) if (SrcIsKill)
// Add an implicit kill for the super-reg. // Add an implicit kill for the super-reg.
(*MIB).addRegisterKilled(SrcReg, TRI, true); (*MIB).addRegisterKilled(SrcReg, TRI, true);
@ -491,8 +504,12 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
// Add the lane number operand. // Add the lane number operand.
MIB.addImm(Lane); MIB.addImm(Lane);
OpIdx += 1;
// Copy the predicate operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addOperand(MI.getOperand(OpIdx++));
MIB = AddDefaultPred(MIB);
// Copy the super-register source to be an implicit source. // Copy the super-register source to be an implicit source.
MO.setImplicit(true); MO.setImplicit(true);
MIB.addOperand(MO); MIB.addOperand(MO);
@ -529,9 +546,12 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MIB.addReg(D3); MIB.addReg(D3);
// Copy the other source register operand. // Copy the other source register operand.
MIB.addOperand(MI.getOperand(OpIdx)); MIB.addOperand(MI.getOperand(OpIdx++));
// Copy the predicate operands.
MIB.addOperand(MI.getOperand(OpIdx++));
MIB.addOperand(MI.getOperand(OpIdx++));
MIB = AddDefaultPred(MIB);
if (SrcIsKill) if (SrcIsKill)
// Add an implicit kill for the super-reg. // Add an implicit kill for the super-reg.
(*MIB).addRegisterKilled(SrcReg, TRI, true); (*MIB).addRegisterKilled(SrcReg, TRI, true);