diff --git a/include/llvm/Pass.h b/include/llvm/Pass.h index 4fd4b2c627f..104b272d095 100644 --- a/include/llvm/Pass.h +++ b/include/llvm/Pass.h @@ -53,7 +53,7 @@ typedef const void* AnalysisID; /// Ordering of pass manager types is important here. enum PassManagerType { PMT_Unknown = 0, - PMT_ModulePassManager = 1, ///< MPPassManager + PMT_ModulePassManager = 1, ///< MPPassManager PMT_CallGraphPassManager, ///< CGPassManager PMT_FunctionPassManager, ///< FPPassManager PMT_LoopPassManager, ///< LPPassManager @@ -84,14 +84,14 @@ class Pass { PassKind Kind; void operator=(const Pass&); // DO NOT IMPLEMENT Pass(const Pass &); // DO NOT IMPLEMENT - + public: explicit Pass(PassKind K, char &pid) : Resolver(0), PassID(&pid), Kind(K) { } virtual ~Pass(); - + PassKind getPassKind() const { return Kind; } - + /// getPassName - Return a nice clean name for a pass. This usually /// implemented in terms of the name that is registered by one of the /// Registration templates, but can be overloaded directly. @@ -119,12 +119,12 @@ public: const std::string &Banner) const = 0; /// Each pass is responsible for assigning a pass manager to itself. - /// PMS is the stack of available pass manager. - virtual void assignPassManager(PMStack &, + /// PMS is the stack of available pass manager. + virtual void assignPassManager(PMStack &, PassManagerType) {} /// Check if available pass managers are suitable for this pass or not. virtual void preparePassManager(PMStack &); - + /// Return what kind of Pass Manager can manage this pass. virtual PassManagerType getPotentialPassManagerType() const; @@ -159,9 +159,9 @@ public: virtual void *getAdjustedAnalysisPointer(AnalysisID ID); virtual ImmutablePass *getAsImmutablePass(); virtual PMDataManager *getAsPMDataManager(); - + /// verifyAnalysis() - This member can be implemented by a analysis pass to - /// check state of analysis information. + /// check state of analysis information. virtual void verifyAnalysis() const; // dumpPassStructure - Implement the -debug-passes=PassStructure option @@ -226,7 +226,7 @@ public: /// being operated on. virtual bool runOnModule(Module &M) = 0; - virtual void assignPassManager(PMStack &PMS, + virtual void assignPassManager(PMStack &PMS, PassManagerType T); /// Return what kind of Pass Manager can manage this pass. @@ -259,9 +259,9 @@ public: /// bool runOnModule(Module &) { return false; } - explicit ImmutablePass(char &pid) + explicit ImmutablePass(char &pid) : ModulePass(pid) {} - + // Force out-of-line virtual method. virtual ~ImmutablePass(); }; @@ -286,7 +286,7 @@ public: /// any necessary per-module initialization. /// virtual bool doInitialization(Module &); - + /// runOnFunction - Virtual method overriden by subclasses to do the /// per-function processing of the pass. /// @@ -297,7 +297,7 @@ public: /// virtual bool doFinalization(Module &); - virtual void assignPassManager(PMStack &PMS, + virtual void assignPassManager(PMStack &PMS, PassManagerType T); /// Return what kind of Pass Manager can manage this pass. @@ -348,7 +348,7 @@ public: /// virtual bool doFinalization(Module &); - virtual void assignPassManager(PMStack &PMS, + virtual void assignPassManager(PMStack &PMS, PassManagerType T); /// Return what kind of Pass Manager can manage this pass. diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 3ce0e824a3f..ae63e767fe5 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -90,7 +90,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock *MBB, std::vector &WorkList) { unsigned BBNum = MBB->getNumber(); - + // Check to see if this basic block is one of the killing blocks. If so, // remove it. for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) @@ -98,7 +98,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo, VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry break; } - + if (MBB == DefBlock) return; // Terminate recursion if (VRInfo.AliveBlocks.test(BBNum)) @@ -329,7 +329,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { // Or whole register is defined, but only partly used. // AX = AL // = AL - // AX = + // AX = MachineInstr *LastPartDef = 0; unsigned LastPartDefDist = 0; SmallSet PartUses; diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 63172f4d54a..bde6690cfa8 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -247,7 +247,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, // If any of the definitions are used by another instruction between the // position and the kill use, then it's not safe to sink it. - // + // // FIXME: This can be sped up if there is an easy way to query whether an // instruction is before or after another instruction. Then we can use // MachineRegisterInfo def / use instead. @@ -290,7 +290,7 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, KillMO->setIsKill(false); KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); KillMO->setIsKill(true); - + if (LV) LV->replaceKillInstruction(SavedReg, KillMI, MI); @@ -336,7 +336,7 @@ TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, continue; // Current use. OtherUse = true; // There is at least one other use in the MBB that will clobber the - // register. + // register. if (isTwoAddrUse(UseMI, Reg)) return true; } @@ -590,7 +590,7 @@ TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, // %reg1029 = MOV8rr %reg1028 // %reg1029 = SHR8ri %reg1029, 7, %EFLAGS // insert => %reg1030 = MOV8rr %reg1029 - // %reg1030 = ADD8rr %reg1029, %reg1028, %EFLAGS + // %reg1030 = ADD8rr %reg1029, %reg1028, %EFLAGS if (!MI->killsRegister(regC)) return false; @@ -906,7 +906,7 @@ TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB, MachineBasicBlock::iterator &nmi, unsigned Reg) { MachineInstr *MI = &*mi; - DenseMap::iterator DI = DistanceMap.find(MI); + DenseMap::iterator DI = DistanceMap.find(MI); if (DI == DistanceMap.end()) // Must be created from unfolded load. Don't waste time trying this. return false; @@ -1334,7 +1334,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi, if (LV) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && + if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { if (MO.isUse()) { if (MO.isKill()) { @@ -1394,7 +1394,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { bool MadeChange = false; DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); - DEBUG(dbgs() << "********** Function: " + DEBUG(dbgs() << "********** Function: " << MF.getFunction()->getName() << '\n'); // This pass takes the function out of SSA form. @@ -1924,7 +1924,7 @@ bool TwoAddressInstructionPass::EliminateRegSequences() { DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) - MI->RemoveOperand(j); + MI->RemoveOperand(j); } else { DEBUG(dbgs() << "Eliminated: " << *MI); MI->eraseFromParent(); diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 919ada7e958..0bbbb0608ce 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -22,7 +22,7 @@ using namespace llvm; extern "C" void LLVMInitializePowerPCTarget() { // Register the targets - RegisterTargetMachine A(ThePPC32Target); + RegisterTargetMachine A(ThePPC32Target); RegisterTargetMachine B(ThePPC64Target); } @@ -46,7 +46,7 @@ bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } void PPC32TargetMachine::anchor() { } -PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -56,7 +56,7 @@ PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, void PPC64TargetMachine::anchor() { } -PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -87,12 +87,12 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, if (Subtarget.isPPC64()) // Temporary workaround for the inability of PPC64 JIT to handle jump // tables. - Options.DisableJumpTables = true; - + Options.DisableJumpTables = true; + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho // writing? Subtarget.SetJITMode(); - + // Machine code emitter pass for PowerPC. PM.add(createPPCJITCodeEmitterPass(*this, JCE)); diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 560de522c84..03147eb0c4c 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -50,7 +50,7 @@ public: return &FrameLowering; } virtual PPCJITInfo *getJITInfo() { return &JITInfo; } - virtual const PPCTargetLowering *getTargetLowering() const { + virtual const PPCTargetLowering *getTargetLowering() const { return &TLInfo; } virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const { @@ -59,10 +59,10 @@ public: virtual const PPCRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } - + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; } - virtual const InstrItineraryData *getInstrItineraryData() const { + virtual const InstrItineraryData *getInstrItineraryData() const { return &InstrItins; } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 88406caaf1c..2a6f4a6a7f7 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -102,7 +102,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, // default to hard float ABI if (Options.FloatABIType == FloatABI::Default) - this->Options.FloatABIType = FloatABI::Hard; + this->Options.FloatABIType = FloatABI::Hard; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 0e0e2bafffe..2bd32b626ba 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -27,7 +27,7 @@ #include "llvm/Target/TargetFrameLowering.h" namespace llvm { - + class formatted_raw_ostream; class StringRef; @@ -38,7 +38,7 @@ class X86TargetMachine : public LLVMTargetMachine { InstrItineraryData InstrItins; public: - X86TargetMachine(const Target &T, StringRef TT, + X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, @@ -57,7 +57,7 @@ public: virtual const X86TargetLowering *getTargetLowering() const { llvm_unreachable("getTargetLowering not implemented"); } - virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { + virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { llvm_unreachable("getSelectionDAGInfo not implemented"); } virtual const X86RegisterInfo *getRegisterInfo() const { @@ -97,7 +97,7 @@ public: virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; } - virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { + virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } virtual const X86InstrInfo *getInstrInfo() const { @@ -126,7 +126,7 @@ public: virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; } - virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { + virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } virtual const X86InstrInfo *getInstrInfo() const { diff --git a/lib/VMCore/Pass.cpp b/lib/VMCore/Pass.cpp index 37e1bf2a8a2..05d2efa850a 100644 --- a/lib/VMCore/Pass.cpp +++ b/lib/VMCore/Pass.cpp @@ -26,8 +26,8 @@ using namespace llvm; // // Force out-of-line virtual method. -Pass::~Pass() { - delete Resolver; +Pass::~Pass() { + delete Resolver; } // Force out-of-line virtual method. @@ -69,7 +69,7 @@ void Pass::preparePassManager(PMStack &) { PassManagerType Pass::getPotentialPassManagerType() const { // Default implementation. - return PMT_Unknown; + return PMT_Unknown; } void Pass::getAnalysisUsage(AnalysisUsage &) const { @@ -153,7 +153,7 @@ PassManagerType FunctionPass::getPotentialPassManagerType() const { Pass *BasicBlockPass::createPrinterPass(raw_ostream &O, const std::string &Banner) const { - + llvm_unreachable("BasicBlockPass printing unsupported."); } @@ -178,7 +178,7 @@ bool BasicBlockPass::doFinalization(Module &) { } PassManagerType BasicBlockPass::getPotentialPassManagerType() const { - return PMT_BasicBlockPassManager; + return PMT_BasicBlockPassManager; } const PassInfo *Pass::lookupPassInfo(const void *TI) { @@ -243,7 +243,7 @@ namespace { typedef AnalysisUsage::VectorType VectorType; VectorType &CFGOnlyList; GetCFGOnlyPasses(VectorType &L) : CFGOnlyList(L) {} - + void passEnumerate(const PassInfo *P) { if (P->isCFGOnlyPass()) CFGOnlyList.push_back(P->getTypeInfo());