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[mips] brcond + setgt/setugt instruction selection patterns.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-06-05 19:49:55 +00:00
parent db9dc53871
commit 8270e68c56
2 changed files with 138 additions and 0 deletions
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4
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1265,6 +1265,10 @@ def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
(BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
(BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;

134
test/CodeGen/Mips/setcc-se.ll
View File

@ -1,5 +1,7 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
@g1 = external global i32
; CHECK: seteq0:
; CHECK: sltiu ${{[0-9]+}}, $4, 1
@ -19,3 +21,135 @@ entry:
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; CHECK: slti_beq0:
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
define void @slti_beq0(i32 %a) {
entry:
%cmp = icmp slt i32 %a, -32768
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: slti_beq1:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq1(i32 %a) {
entry:
%cmp = icmp slt i32 %a, -32769
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: slti_beq2:
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
define void @slti_beq2(i32 %a) {
entry:
%cmp = icmp slt i32 %a, 32767
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: slti_beq3:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq3(i32 %a) {
entry:
%cmp = icmp slt i32 %a, 32768
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: sltiu_beq0:
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
define void @sltiu_beq0(i32 %a) {
entry:
%cmp = icmp ult i32 %a, 32767
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: sltiu_beq1:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq1(i32 %a) {
entry:
%cmp = icmp ult i32 %a, 32768
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: sltiu_beq2:
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
define void @sltiu_beq2(i32 %a) {
entry:
%cmp = icmp ult i32 %a, -32768
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}
; CHECK: sltiu_beq3:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq3(i32 %a) {
entry:
%cmp = icmp ult i32 %a, -32769
br i1 %cmp, label %if.then, label %if.end
if.then:
store i32 %a, i32* @g1, align 4
br label %if.end
if.end:
ret void
}