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Add the rest of the logical instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18148 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -100,12 +100,30 @@ let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ANDCCrr : F3_1<2, 0b010001, "andcc">;
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def ANDCCri : F3_2<2, 0b010001, "andcc">;
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def ANDNrr : F3_1<2, 0b000101, "andn">;
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def ANDNri : F3_2<2, 0b000101, "andn">;
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def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
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def ANDNCCri: F3_2<2, 0b010101, "andncc">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def ORCCrr : F3_1<2, 0b010010, "orcc">;
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def ORCCri : F3_2<2, 0b010010, "orcc">;
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def ORNrr : F3_1<2, 0b000110, "orn">;
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def ORNri : F3_2<2, 0b000110, "orn">;
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def ORNCCrr : F3_1<2, 0b010110, "orncc">;
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def ORNCCri : F3_2<2, 0b010110, "orncc">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def XORCCrr : F3_1<2, 0b010011, "xorcc">;
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def XORCCri : F3_2<2, 0b010011, "xorcc">;
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def XNORrr : F3_1<2, 0b000111, "xnor">;
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def XNORri : F3_2<2, 0b000111, "xnor">;
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def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
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def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101, "sll">;
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@ -100,12 +100,30 @@ let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ANDCCrr : F3_1<2, 0b010001, "andcc">;
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def ANDCCri : F3_2<2, 0b010001, "andcc">;
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def ANDNrr : F3_1<2, 0b000101, "andn">;
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def ANDNri : F3_2<2, 0b000101, "andn">;
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def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
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def ANDNCCri: F3_2<2, 0b010101, "andncc">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def ORCCrr : F3_1<2, 0b010010, "orcc">;
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def ORCCri : F3_2<2, 0b010010, "orcc">;
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def ORNrr : F3_1<2, 0b000110, "orn">;
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def ORNri : F3_2<2, 0b000110, "orn">;
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def ORNCCrr : F3_1<2, 0b010110, "orncc">;
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def ORNCCri : F3_2<2, 0b010110, "orncc">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def XORCCrr : F3_1<2, 0b010011, "xorcc">;
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def XORCCri : F3_2<2, 0b010011, "xorcc">;
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def XNORrr : F3_1<2, 0b000111, "xnor">;
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def XNORri : F3_2<2, 0b000111, "xnor">;
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def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
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def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101, "sll">;
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