6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 21:32:10 +00:00
Code Issues Projects Releases Wiki Activity

Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-02-19 05:34:21 +00:00
parent b7e1ab7959
commit 82a644adf2
11 changed files with 122 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
View File

@ -73,12 +73,6 @@ static int modRMRequired(OpcodeType type,
case THREEBYTE_3A:
decision = &THREEBYTE3A_SYM;
break;
case THREEBYTE_A6:
decision = &THREEBYTEA6_SYM;
break;
case THREEBYTE_A7:
decision = &THREEBYTEA7_SYM;
break;
case XOP8_MAP:
decision = &XOP8_MAP_SYM;
break;
@ -123,12 +117,6 @@ static InstrUID decode(OpcodeType type,
case THREEBYTE_3A:
dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case THREEBYTE_A6:
dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case THREEBYTE_A7:
dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
case XOP8_MAP:
dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
break;
@ -768,20 +756,6 @@ static int readOpcode(struct InternalInstruction* insn) {
return -1;
insn->opcodeType = THREEBYTE_3A;
} else if (current == 0xa6) {
dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
if (consumeByte(insn, &current))
return -1;
insn->opcodeType = THREEBYTE_A6;
} else if (current == 0xa7) {
dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
if (consumeByte(insn, &current))
return -1;
insn->opcodeType = THREEBYTE_A7;
} else {
dbgprintf(insn, "Didn't find a three-byte escape prefix");

12
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
View File

@ -30,8 +30,6 @@
#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
#define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
#define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
@ -42,8 +40,6 @@
#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
#define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes"
#define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes"
#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
@ -293,11 +289,9 @@ typedef enum {
TWOBYTE = 1,
THREEBYTE_38 = 2,
THREEBYTE_3A = 3,
THREEBYTE_A6 = 4,
THREEBYTE_A7 = 5,
XOP8_MAP = 6,
XOP9_MAP = 7,
XOPA_MAP = 8
XOP8_MAP = 4,
XOP9_MAP = 5,
XOPA_MAP = 6
} OpcodeType;
/*

35
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -290,13 +290,13 @@ namespace X86II {
MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
//// MRM_XX - A mod/rm byte of exactly 0xXX.
MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36,
MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39, MRM_CB = 40,
MRM_E8 = 41, MRM_F0 = 42, MRM_F8 = 45, MRM_F9 = 46,
MRM_D0 = 47, MRM_D1 = 48, MRM_D4 = 49, MRM_D5 = 50,
MRM_D6 = 51, MRM_D8 = 52, MRM_D9 = 53, MRM_DA = 54,
MRM_DB = 55, MRM_DC = 56, MRM_DD = 57, MRM_DE = 58,
MRM_DF = 59,
MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35,
MRM_C4 = 36, MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39,
MRM_CB = 40, MRM_E8 = 41, MRM_F0 = 42, MRM_F8 = 45,
MRM_F9 = 46, MRM_D0 = 47, MRM_D1 = 48, MRM_D4 = 49,
MRM_D5 = 50, MRM_D6 = 51, MRM_D8 = 52, MRM_D9 = 53,
MRM_DA = 54, MRM_DB = 55, MRM_DC = 56, MRM_DD = 57,
MRM_DE = 58, MRM_DF = 59, MRM_E0 = 60,
/// RawFrmImm8 - This is used for the ENTER instruction, which has two
/// immediates, the first of which is a 16-bit immediate (specified by
@ -378,9 +378,6 @@ namespace X86II {
DC = 11 << OpMapShift, DD = 12 << OpMapShift,
DE = 13 << OpMapShift, DF = 14 << OpMapShift,
// A6, A7 - Prefix after the 0x0F prefix.
A6 = 15 << OpMapShift, A7 = 16 << OpMapShift,
//===------------------------------------------------------------------===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
// They are used to specify GPRs and SSE registers, 64-bit operand size,
@ -695,15 +692,15 @@ namespace X86II {
++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV).
return FirstMemOp;
}
case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_E8:
case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_DF:
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
case X86II::MRM_F9: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
return -1;
}
}

28
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -1150,8 +1150,6 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::TB: // Two-byte opcode map
case X86II::T8: // 0F 38
case X86II::TA: // 0F 3A
case X86II::A6: // 0F A6
case X86II::A7: // 0F A7
EmitByte(0x0F, CurByte, OS);
break;
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
@ -1168,12 +1166,6 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::TA: // 0F 3A
EmitByte(0x3A, CurByte, OS);
break;
case X86II::A6: // 0F A6
EmitByte(0xA6, CurByte, OS);
break;
case X86II::A7: // 0F A7
EmitByte(0xA7, CurByte, OS);
break;
}
}
@ -1456,20 +1448,21 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
CurOp += X86::AddrNumOperands;
break;
}
case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
case X86II::MRM_F9:
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8:
case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9:
EmitByte(BaseOpcode, CurByte, OS);
unsigned char MRM;
switch (TSFlags & X86II::FormMask) {
default: llvm_unreachable("Invalid Form");
case X86II::MRM_C0: MRM = 0xC0; break;
case X86II::MRM_C1: MRM = 0xC1; break;
case X86II::MRM_C2: MRM = 0xC2; break;
case X86II::MRM_C3: MRM = 0xC3; break;
@ -1491,6 +1484,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_DD: MRM = 0xDD; break;
case X86II::MRM_DE: MRM = 0xDE; break;
case X86II::MRM_DF: MRM = 0xDF; break;
case X86II::MRM_E0: MRM = 0xE0; break;
case X86II::MRM_E8: MRM = 0xE8; break;
case X86II::MRM_F0: MRM = 0xF0; break;
case X86II::MRM_F8: MRM = 0xF8; break;

27
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -682,8 +682,6 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
case X86II::TB: // Two-byte opcode map
case X86II::T8: // 0F 38
case X86II::TA: // 0F 3A
case X86II::A6: // 0F A6
case X86II::A7: // 0F A7
MCE.emitByte(0x0F);
break;
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
@ -701,12 +699,6 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
case X86II::TA: // 0F 3A
MCE.emitByte(0x3A);
break;
case X86II::A6: // 0F A6
MCE.emitByte(0xA6);
break;
case X86II::A7: // 0F A7
MCE.emitByte(0xA7);
break;
}
}
@ -1379,19 +1371,21 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
break;
}
case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8:
case X86II::MRM_F0: case X86II::MRM_F8:
MCE.emitByte(BaseOpcode);
unsigned char MRM;
switch (TSFlags & X86II::FormMask) {
default: llvm_unreachable("Invalid Form");
case X86II::MRM_C0: MRM = 0xC0; break;
case X86II::MRM_C1: MRM = 0xC1; break;
case X86II::MRM_C2: MRM = 0xC2; break;
case X86II::MRM_C3: MRM = 0xC3; break;
@ -1413,6 +1407,7 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRM_DD: MRM = 0xDD; break;
case X86II::MRM_DE: MRM = 0xDE; break;
case X86II::MRM_DF: MRM = 0xDF; break;
case X86II::MRM_E0: MRM = 0xE0; break;
case X86II::MRM_E8: MRM = 0xE8; break;
case X86II::MRM_F0: MRM = 0xF0; break;
case X86II::MRM_F8: MRM = 0xF8; break;

6
lib/Target/X86/X86InstrFormats.td
View File

@ -31,6 +31,7 @@ def MRM6r : Format<22>; def MRM7r : Format<23>;
def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
def MRM6m : Format<30>; def MRM7m : Format<31>;
def MRM_C0 : Format<32>;
def MRM_C1 : Format<33>;
def MRM_C2 : Format<34>;
def MRM_C3 : Format<35>;
@ -58,6 +59,7 @@ def MRM_DC : Format<56>;
def MRM_DD : Format<57>;
def MRM_DE : Format<58>;
def MRM_DF : Format<59>;
def MRM_E0 : Format<60>;
// ImmType - This specifies the immediate type used by an instruction. This is
// part of the ad-hoc solution used to emit machine instruction encodings by our
@ -142,8 +144,6 @@ def DC : Map<11>;
def DD : Map<12>;
def DE : Map<13>;
def DF : Map<14>;
def A6 : Map<15>;
def A7 : Map<16>;
// Class specifying the encoding
class Encoding<bits<2> val> {
@ -181,8 +181,6 @@ class DE { Map OpMap = DE; }
class DF { Map OpMap = DF; }
class T8 { Map OpMap = T8; }
class TA { Map OpMap = TA; }
class A6 { Map OpMap = A6; }
class A7 { Map OpMap = A7; }
class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }

18
lib/Target/X86/X86InstrSystem.td
View File

@ -507,24 +507,24 @@ let Uses = [RDX, RAX] in {
//===----------------------------------------------------------------------===//
// VIA PadLock crypto instructions
let Defs = [RAX, RDI], Uses = [RDX, RDI] in
def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
def : InstAlias<"xstorerng", (XSTORE)>;
let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
}
let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
}
let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
//===----------------------------------------------------------------------===//
// FS/GS Base Instructions

56
test/MC/Disassembler/X86/padlock.txt Normal file
View File

@ -0,0 +1,56 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
# CHECK: xstore
0x0f 0xa7 0xc0
# CHECK: xcryptecb
0x0f 0xa7 0xc8
# CHECK: xcryptcbc
0x0f 0xa7 0xd0
# CHECK: xcryptctr
0x0f 0xa7 0xd8
# CHECK: xcryptcfb
0x0f 0xa7 0xe0
# CHECK: xcryptofb
0x0f 0xa7 0xe8
# CHECK: xsha1
0x0f 0xa6 0xc8
# CHECK: xsha256
0x0f 0xa6 0xd0
# CHECK: montmul
0x0f 0xa6 0xc0
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
# CHECK: xstore
0x0f 0xa7 0xc0
# CHECK: xcryptecb
0x0f 0xa7 0xc8
# CHECK: xcryptcbc
0x0f 0xa7 0xd0
# CHECK: xcryptctr
0x0f 0xa7 0xd8
# CHECK: xcryptcfb
0x0f 0xa7 0xe0
# CHECK: xcryptofb
0x0f 0xa7 0xe8
# CHECK: xsha1
0x0f 0xa6 0xc8
# CHECK: xsha256
0x0f 0xa6 0xd0
# CHECK: montmul
0x0f 0xa6 0xc0

8
utils/TableGen/X86DisassemblerTables.cpp
View File

@ -737,11 +737,9 @@ void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
}
void DisassemblerTables::emit(raw_ostream &o) const {

13
utils/TableGen/X86DisassemblerTables.h
View File

@ -38,12 +38,10 @@ private:
/// [1] two-byte opcodes of the form 0f __
/// [2] three-byte opcodes of the form 0f 38 __
/// [3] three-byte opcodes of the form 0f 3a __
/// [4] three-byte opcodes of the form 0f a6 __
/// [5] three-byte opcodes of the form 0f a7 __
/// [6] XOP8 map opcode
/// [7] XOP9 map opcode
/// [8] XOPA map opcode
ContextDecision* Tables[9];
/// [4] XOP8 map opcode
/// [5] XOP9 map opcode
/// [6] XOPA map opcode
ContextDecision* Tables[7];
// Table of ModRM encodings.
typedef std::map<std::vector<unsigned>, unsigned> ModRMMapTy;
@ -132,8 +130,7 @@ private:
/// }
///
/// NAME is the name of the ContextDecision (typically one of the four names
/// ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
/// THREEBYTEA6_SYM, and THREEBYTEA7_SYM from
/// ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM from
/// X86DisassemblerDecoderCommon.h).
/// IC is one of the contexts in InstructionContext. There is an opcode
/// decision for each possible context.

13
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -23,6 +23,7 @@
using namespace llvm;
#define MRM_MAPPING \
MAP(C0, 32) \
MAP(C1, 33) \
MAP(C2, 34) \
MAP(C3, 35) \
@ -47,7 +48,8 @@ using namespace llvm;
MAP(DC, 56) \
MAP(DD, 57) \
MAP(DE, 58) \
MAP(DF, 59)
MAP(DF, 59) \
MAP(E0, 60)
// A clone of X86 since we can't depend on something that is generated.
namespace X86Local {
@ -79,8 +81,7 @@ namespace X86Local {
enum {
OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
D8 = 7, D9 = 8, DA = 9, DB = 10,
DC = 11, DD = 12, DE = 13, DF = 14,
A6 = 15, A7 = 16
DC = 11, DD = 12, DE = 13, DF = 14
};
enum {
@ -731,6 +732,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPERAND(relocation)
}
break;
case X86Local::MRM_C0:
case X86Local::MRM_C1:
case X86Local::MRM_C2:
case X86Local::MRM_C3:
@ -755,6 +757,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
case X86Local::MRM_DD:
case X86Local::MRM_DE:
case X86Local::MRM_DF:
case X86Local::MRM_E0:
// Ignored.
break;
}
@ -782,8 +785,6 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::TB:
case X86Local::T8:
case X86Local::TA:
case X86Local::A6:
case X86Local::A7:
case X86Local::XOP8:
case X86Local::XOP9:
case X86Local::XOPA:
@ -793,8 +794,6 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::TB: opcodeType = TWOBYTE; break;
case X86Local::T8: opcodeType = THREEBYTE_38; break;
case X86Local::TA: opcodeType = THREEBYTE_3A; break;
case X86Local::A6: opcodeType = THREEBYTE_A6; break;
case X86Local::A7: opcodeType = THREEBYTE_A7; break;
case X86Local::XOP8: opcodeType = XOP8_MAP; break;
case X86Local::XOP9: opcodeType = XOP9_MAP; break;
case X86Local::XOPA: opcodeType = XOPA_MAP; break;