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Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117699 91177308-0d34-0410-b5e6-96231b3b80d8
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Owen Anderson
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; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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; XFAIL: *
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declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
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; CHECK: vrecpe_2xi32
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define <2 x i32> @vrecpe_2xi32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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; CHECK: vrecpe_4xi32
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define <4 x i32> @vrecpe_4xi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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; CHECK: vrecpe_2xfloat
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define <2 x float> @vrecpe_2xfloat(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
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%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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; CHECK: vrecpe_4xfloat
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define <4 x float> @vrecpe_4xfloat(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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; CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
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%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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; CHECK: vrecps_2xfloat
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define <2 x float> @vrecps_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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; CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
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%tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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; CHECK: vrecps_4xfloat
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define <4 x float> @vrecps_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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; CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
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%tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
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; CHECK: vrsqrte_2xi32
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define <2 x i32> @vrsqrte_2xi32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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; CHECK: vrsqrte_4xi32
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define <4 x i32> @vrsqrte_4xi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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; CHECK: vrsqrte_2xfloat
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define <2 x float> @vrsqrte_2xfloat(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
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%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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; CHECK: vrsqrte_4xfloat
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define <4 x float> @vrsqrte_4xfloat(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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; CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
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%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
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; CHECK: vrsqrts_2xfloat
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define <2 x float> @vrsqrts_2xfloat(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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; CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
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%tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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; CHECK: vrsqrts_4xfloat
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define <4 x float> @vrsqrts_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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; CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
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%tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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26
test/MC/ARM/neon-reciprocal-encoding.s
Normal file
26
test/MC/ARM/neon-reciprocal-encoding.s
Normal file
@ -0,0 +1,26 @@
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// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
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// CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
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vrecpe.u32 d16, d16
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// CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
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vrecpe.u32 q8, q8
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// CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
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vrecpe.f32 d16, d16
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// CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
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vrecpe.f32 q8, q8
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// CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
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vrecps.f32 d16, d16, d17
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// CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
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vrecps.f32 q8, q8, q9
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// CHECK: vrsqrte.u32 d16, d16 @ encoding: [0xa0,0x04,0xfb,0xf3]
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vrsqrte.u32 d16, d16
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// CHECK: vrsqrte.u32 q8, q8 @ encoding: [0xe0,0x04,0xfb,0xf3]
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vrsqrte.u32 q8, q8
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// CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
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vrsqrte.f32 d16, d16
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// CHECK: vrsqrte.f32 q8, q8 @ encoding: [0xe0,0x05,0xfb,0xf3]
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vrsqrte.f32 q8, q8
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// CHECK: vrsqrts.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x60,0xf2]
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vrsqrts.f32 d16, d16, d17
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// CHECK: vrsqrts.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x60,0xf2]
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vrsqrts.f32 q8, q8, q9
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