6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 06:33:24 +00:00
Code Issues Projects Releases Wiki Activity

Added support for handling unpredictable arithmetic instructions on ARM.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-04-05 16:13:15 +00:00
parent 940371bc65
commit 82e1bba0e4
3 changed files with 9 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3244,6 +3244,8 @@ class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{3-0} = Rm;
let Unpredictable{11-8} = 0b1111;
}
// Saturating add/subtract

12
test/MC/Disassembler/ARM/invalid-LDRT-arm.txt
View File

@ -1,12 +0,0 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction.
0x10 0x51 0x37 0xe6

7
test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# CHECK: warning: potentially undefined
# CHECK: shadd16 r5, r7, r0
0x10 0x51 0x37 0xe6