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On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.

Browse Source 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
John McCall 2011-05-29 19:39:04 +00:00
parent bcb85087a7
commit 832a9d1a76
5 changed files with 40 additions and 1 deletions
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3
autoconf/configure.ac
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@ -605,7 +605,7 @@ if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Glulx Mips CellSPU XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@ -614,6 +614,7 @@ case "$enableval" in
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
glulx) TARGETS_TO_BUILD="Glulx $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;

1
include/llvm/ADT/Triple.h
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@ -50,6 +50,7 @@ public:
arm, // ARM; arm, armv.*, xscale
bfin, // Blackfin: bfin
cellspu, // CellSPU: spu, cellspu
glulx, // Glulx: glulx, glulx1, glulx2, glulx3
mips, // MIPS: mips, mipsallegrex
mipsel, // MIPSEL: mipsel, mipsallegrexel, psp
msp430, // MSP430: msp430

7
lib/Support/Triple.cpp
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@ -27,6 +27,7 @@ const char *Triple::getArchTypeName(ArchType Kind) {
case arm: return "arm";
case bfin: return "bfin";
case cellspu: return "cellspu";
case glulx: return "glulx";
case mips: return "mips";
case mipsel: return "mipsel";
case msp430: return "msp430";
@ -62,6 +63,8 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
case cellspu: return "spu";
case glulx: return "glulx";
case ppc64:
case ppc: return "ppc";
@ -139,6 +142,8 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
return bfin;
if (Name == "cellspu")
return cellspu;
if (Name == "glulx")
return glulx;
if (Name == "mips")
return mips;
if (Name == "mipsel")
@ -277,6 +282,8 @@ Triple::ArchType Triple::ParseArch(StringRef ArchName) {
return thumb;
else if (ArchName.startswith("alpha"))
return alpha;
else if (ArchName.startswith("glulx"))
return glulx;
else if (ArchName == "spu" || ArchName == "cellspu")
return cellspu;
else if (ArchName == "msp430")

1
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -656,6 +656,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
}
setOperationAction(ISD::SETCC, MVT::i32, Expand);

29
test/CodeGen/ARM/eh-resume-darwin.ll Normal file
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@ -0,0 +1,29 @@
; RUN: llc < %s -march=arm | FileCheck %s
target triple = "armv6-apple-macosx10.6"
declare void @func()
declare i8* @llvm.eh.exception() nounwind readonly
declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind
declare void @llvm.eh.resume(i8*, i32)
declare i32 @__gxx_personality_sj0(...)
define void @test0() {
entry:
invoke void @func()
to label %cont unwind label %lpad
cont:
ret void
lpad:
%exn = call i8* @llvm.eh.exception()
%sel = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0)
call void @llvm.eh.resume(i8* %exn, i32 %sel) noreturn
unreachable
}
; CHECK: __Unwind_SjLj_Resume