6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-12 18:33:22 +00:00
Code Issues Projects Releases Wiki Activity

CopyToReg source operand can be a physical register.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35213 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lauro Ramos Venancio 2007-03-20 16:46:44 +00:00
parent 3a7f7ab73f
commit 8334b9fa3b
1 changed files with 19 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -475,9 +475,25 @@ void ScheduleDAG::EmitNode(SDNode *Node,
else
InReg = getVR(Node->getOperand(2), VRBaseMap);
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (InReg != DestReg) // Coalesced away the copy?
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
RegMap->getRegClass(InReg));
if (InReg != DestReg) {// Coalesced away the copy?
const TargetRegisterClass *TRC = 0;
// Get the target register class
if (MRegisterInfo::isVirtualRegister(InReg)) {
TRC = RegMap->getRegClass(InReg);
} else {
// Pick the register class of the right type that contains this
// physreg.
for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
E = MRI->regclass_end(); I != E; ++I)
if ((*I)->hasType(Node->getOperand(2).getValueType()) &&
(*I)->contains(InReg)) {
TRC = *I;
break;
}
assert(TRC && "Couldn't find register class for reg copy!");
}
MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
}
break;
}
case ISD::CopyFromReg: {