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[Sparc] Add fcmpe* instructions to Sparc backend.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2014-03-02 19:56:19 +00:00
parent cf06410678
commit 833687be0e
5 changed files with 49 additions and 6 deletions
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14
lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
View File

@ -69,9 +69,8 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
return true;
}
}
case SP::V9FCMPS:
case SP::V9FCMPD:
case SP::V9FCMPQ: {
case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
if (isV9()
|| (MI->getNumOperands() != 3)
|| (!MI->getOperand(0).isReg())
@ -80,9 +79,12 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
// if V8, skip printing %fcc0.
switch(MI->getOpcode()) {
default:
case SP::V9FCMPS: O << "\tfcmps "; break;
case SP::V9FCMPD: O << "\tfcmpd "; break;
case SP::V9FCMPQ: O << "\tfcmpq "; break;
case SP::V9FCMPS: O << "\tfcmps "; break;
case SP::V9FCMPD: O << "\tfcmpd "; break;
case SP::V9FCMPQ: O << "\tfcmpq "; break;
case SP::V9FCMPES: O << "\tfcmpes "; break;
case SP::V9FCMPED: O << "\tfcmped "; break;
case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
}
printOperand(MI, 1, O);
O << ", ";

7
lib/Target/Sparc/SparcInstrAliases.td
View File

@ -260,3 +260,10 @@ def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
Requires<[HasHardQuad]>;
def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
DFPRegs:$rs2)>;
def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
QFPRegs:$rs2)>,
Requires<[HasHardQuad]>;

13
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -1040,6 +1040,19 @@ def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
"fcmpq $rd, $rs1, $rs2", []>,
Requires<[HasHardQuad]>;
let hasSideEffects = 1 in {
def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
(outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fcmpes $rd, $rs1, $rs2", []>;
def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
(outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fcmped $rd, $rs1, $rs2", []>;
def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
(outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"fcmpeq $rd, $rs1, $rs2", []>,
Requires<[HasHardQuad]>;
}
// Floating point conditional move instrucitons with %fcc0-%fcc3.
let Predicates = [HasV9] in {
let Constraints = "$f = $rd", intcc = 0 in {

14
test/MC/Sparc/sparc-fp-instructions.s
View File

@ -103,6 +103,13 @@
fcmpd %f0, %f4
fcmpq %f0, %f4
! CHECK: fcmpes %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
! CHECK: fcmped %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
! CHECK: fcmpeq %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
fcmpes %f0, %f4
fcmped %f0, %f4
fcmpeq %f0, %f4
! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]
! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]
! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]
@ -110,6 +117,13 @@
fcmpd %fcc2, %f0, %f4
fcmpq %fcc2, %f0, %f4
! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]
! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]
! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]
fcmpes %fcc2, %f0, %f4
fcmped %fcc2, %f0, %f4
fcmpeq %fcc2, %f0, %f4
! CHECK: fxtos %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x80]
! CHECK: fxtod %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x00]
! CHECK: fxtoq %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x80]

7
test/MC/Sparc/sparcv8-instructions.s
View File

@ -6,3 +6,10 @@
fcmps %f0, %f4
fcmpd %f0, %f4
fcmpq %f0, %f4
! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
fcmpes %f0, %f4
fcmped %f0, %f4
fcmpeq %f0, %f4