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Mark ARM subtarget features that are available for the assembler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-11-01 16:59:54 +00:00
parent d4462a5a4f
commit 833c93c795
23 changed files with 42 additions and 36 deletions
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30
lib/Target/ARM/ARMInstrInfo.td
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@@ -142,27 +142,29 @@ def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions. // ARM Instruction Predicate Definitions.
// //
def HasV4T : Predicate<"Subtarget->hasV4TOps()">; def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
def HasV5T : Predicate<"Subtarget->hasV5TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
def HasV6 : Predicate<"Subtarget->hasV6Ops()">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
def HasV7 : Predicate<"Subtarget->hasV7Ops()">; def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
def HasNEON : Predicate<"Subtarget->hasNEON()">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
def HasDivide : Predicate<"Subtarget->hasDivide()">; def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">; def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
def HasDB : Predicate<"Subtarget->hasDataBarrier()">; AssemblerPredicate;
def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
AssemblerPredicate;
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
def IsThumb : Predicate<"Subtarget->isThumb()">; def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
def IsThumb2 : Predicate<"Subtarget->isThumb2()">; def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
def IsARM : Predicate<"!Subtarget->isThumb()">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;

6
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -92,7 +92,11 @@ private:
public: public:
ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
: TargetAsmParser(T), Parser(_Parser), TM(_TM) {} : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(
&TM.getSubtarget<ARMSubtarget>()));
}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands); SmallVectorImpl<MCParsedAsmOperand*> &Operands);

2
test/MC/ARM/arm_instructions.s
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@@ -1,4 +1,4 @@
@ RUN: llvm-mc -triple arm-unknown-unknown -show-encoding %s | FileCheck %s @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
@ CHECK: nop @ CHECK: nop
@ CHECK: encoding: [0x00,0xf0,0x20,0xe3] @ CHECK: encoding: [0x00,0xf0,0x20,0xe3]

2
test/MC/ARM/arm_word_directive.s
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@@ -1,4 +1,4 @@
@ RUN: llvm-mc -triple arm-unknown-unknown %s | FileCheck %s @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown %s | FileCheck %s
@ CHECK: TEST0: @ CHECK: TEST0:
@ CHECK: .long 3 @ CHECK: .long 3

2
test/MC/ARM/neon-abs-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3] // CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xf3]
vabs.s8 d16, d16 vabs.s8 d16, d16

2
test/MC/ARM/neon-absdiff-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// NOTE: This currently fails because the ASM parser doesn't parse vabal. // NOTE: This currently fails because the ASM parser doesn't parse vabal.

2
test/MC/ARM/neon-add-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
// CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2] // CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf2]

2
test/MC/ARM/neon-bitcount-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] // CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3]

2
test/MC/ARM/neon-bitwise-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] // CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2]
vand d16, d17, d16 vand d16, d17, d16

2
test/MC/ARM/neon-cmp-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// FIXME: We cannot currently test the following instructions, which are // FIXME: We cannot currently test the following instructions, which are

2
test/MC/ARM/neon-convert-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3] // CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
vcvt.s32.f32 d16, d16 vcvt.s32.f32 d16, d16

2
test/MC/ARM/neon-dup-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] // CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee]

2
test/MC/ARM/neon-minmax-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2] // CHECK: vmin.s8 d16, d16, d17 @ encoding: [0xb1,0x06,0x40,0xf2]
vmin.s8 d16, d16, d17 vmin.s8 d16, d16, d17

2
test/MC/ARM/neon-mov-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] // CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]

2
test/MC/ARM/neon-mul-accum-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] // CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2]

2
test/MC/ARM/neon-mul-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] // CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2]
vmul.i8 d16, d16, d17 vmul.i8 d16, d16, d17

2
test/MC/ARM/neon-neg-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] // CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3]
vneg.s8 d16, d16 vneg.s8 d16, d16

2
test/MC/ARM/neon-pairwise-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// XFAIL: * // XFAIL: *
// CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] // CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2]

2
test/MC/ARM/neon-reciprocal-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3] // CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
vrecpe.u32 d16, d16 vrecpe.u32 d16, d16

2
test/MC/ARM/neon-reverse-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3] // CHECK: vrev64.8 d16, d16 @ encoding: [0x20,0x00,0xf0,0xf3]
vrev64.8 d16, d16 vrev64.8 d16, d16

2
test/MC/ARM/neon-satshift-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2] // CHECK: vqshl.s8 d16, d16, d17 @ encoding: [0xb0,0x04,0x41,0xf2]
vqshl.s8 d16, d16, d17 vqshl.s8 d16, d16, d17

2
test/MC/ARM/neon-shift-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
// CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] // CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3]
vshl.u8 d16, d17, d16 vshl.u8 d16, d17, d16

2
test/MC/ARM/simple-fp-encoding.s
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@@ -1,4 +1,4 @@
// RUN: llvm-mc -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s // RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
// CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] // CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
vadd.f64 d16, d17, d16 vadd.f64 d16, d17, d16