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MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -174,6 +174,18 @@ class SHILO_R2_FMT<bits<5> op> : DSPInst {
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let Inst{5-0} = 0b111000;
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}
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class RDDSP_FMT<bits<5> op> : DSPInst {
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bits<5> rd;
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bits<10> mask;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-16} = mask;
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let Inst{15-11} = rd;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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class BPOSGE32_FMT<bits<5> op> : DSPInst {
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bits<16> offset;
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@ -164,6 +164,7 @@ class SHILO_ENC : SHILO_R1_FMT<0b11010>;
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class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
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class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
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class RDDSP_ENC : RDDSP_FMT<0b10010>;
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class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
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class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
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class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
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@ -296,6 +297,16 @@ class MTHLIP_DESC_BASE<string instr_asm> {
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string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
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}
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class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin> {
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dag OutOperandList = (outs CPURegs:$rd);
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dag InOperandList = (ins uimm16:$mask);
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string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
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list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
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InstrItinClass Itinerary = itin;
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list<Register> Uses = [DSPCtrl];
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}
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class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin,
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Instruction realinst> :
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PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt),
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@ -573,6 +584,8 @@ class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">;
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class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">;
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class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
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//===----------------------------------------------------------------------===//
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// MIPS DSP Rev 2
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// Addition/subtraction
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@ -719,6 +732,7 @@ def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
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def SHILO : SHILO_ENC, SHILO_DESC;
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def SHILOV : SHILOV_ENC, SHILOV_DESC;
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def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
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def RDDSP : RDDSP_ENC, RDDSP_DESC;
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// MIPS DSP Rev 2
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let Predicates = [HasDSPR2] in {
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