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Second attempt at providing correct encodings for Thumb2 binary operators.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2010-11-14 05:37:38 +00:00
parent 1f4f9e3d35
commit 83da6cd5e2
1 changed files with 105 additions and 51 deletions
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156
lib/Target/ARM/ARMInstrThumb2.td
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@@ -170,7 +170,21 @@ def t2addrmode_so_reg : Operand<i32>,
// Multiclass helpers... // Multiclass helpers...
// //
class T2TwoRegShiftedImm<dag oops, dag iops, InstrItinClass itin, class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{11-8} = Rd{3-0};
let Inst{19-16} = Rn{3-0};
let Inst{26} = imm{11};
let Inst{14-12} = imm{10-8};
let Inst{7-0} = imm{7-0};
}
class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> { : T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd; bits<4> Rd;
@@ -186,6 +200,18 @@ class T2TwoRegShiftedImm<dag oops, dag iops, InstrItinClass itin,
class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-8} = Rd{3-0};
let Inst{19-16} = Rn{3-0};
let Inst{3-0} = Rm{3-0};
}
class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> { : T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd; bits<4> Rd;
bits<4> Rn; bits<4> Rn;
@@ -198,6 +224,21 @@ class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rn;
bits<12> ShiftedRm;
let Inst{11-8} = Rd{3-0};
let Inst{19-16} = Rn{3-0};
let Inst{3-0} = ShiftedRm{3-0};
let Inst{5-4} = ShiftedRm{6-5};
let Inst{14-12} = ShiftedRm{11-9};
let Inst{7-6} = ShiftedRm{8-7};
}
class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2sI<oops, iops, itin, opc, asm, pattern> { : T2sI<oops, iops, itin, opc, asm, pattern> {
bits<4> Rd; bits<4> Rd;
bits<4> Rn; bits<4> Rn;
@@ -262,9 +303,10 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
PatFrag opnode, bit Commutable = 0, string wide = ""> { PatFrag opnode, bit Commutable = 0, string wide = ""> {
// shifted imm // shifted imm
def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii, def ri : T2sTwoRegImm<
opc, "\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { opc, "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -272,9 +314,9 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir, def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
[(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
@@ -285,9 +327,10 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis, def rs : T2sTwoRegShiftedReg<
opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
[(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -307,9 +350,10 @@ multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
/// it is equivalent to the T2I_bin_irs counterpart. /// it is equivalent to the T2I_bin_irs counterpart.
multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, def ri : T2sTwoRegImm<
opc, ".w\t$dst, $rhs, $lhs", (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
[(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { opc, ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -317,8 +361,9 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, def rr : T2sThreeReg<
opc, "\t$dst, $rhs, $lhs", (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, "\t$Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
@@ -329,9 +374,10 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsir, def rs : T2sTwoRegShiftedReg<
opc, "\t$dst, $rhs, $lhs", (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
[(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -346,9 +392,10 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
PatFrag opnode, bit Commutable = 0> { PatFrag opnode, bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii, def ri : T2TwoRegImm<
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -356,9 +403,10 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir, def rr : T2ThreeReg<
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
[(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
@@ -369,9 +417,10 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis, def rs : T2TwoRegShiftedReg<
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -388,9 +437,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
// The register-immediate version is re-materializable. This is useful // The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local. // in particular for taking the address of a local.
let isReMaterializable = 1 in { let isReMaterializable = 1 in {
def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, def ri : T2sTwoRegImm<
opc, ".w\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { opc, ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24} = 1; let Inst{24} = 1;
@@ -400,9 +450,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
} }
} }
// 12-bit imm // 12-bit imm
def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, def ri12 : T2TwoRegImm<
!strconcat(opc, "w"), "\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
[(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24} = 0; let Inst{24} = 0;
@@ -411,9 +462,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr, def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, ".w\t$dst, $lhs, $rhs", opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
@@ -425,9 +476,10 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, def rs : T2sTwoRegShiftedReg<
opc, ".w\t$dst, $lhs, $rhs", (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
[(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24} = 1; let Inst{24} = 1;
@@ -443,7 +495,7 @@ let Uses = [CPSR] in {
multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2TwoRegShiftedImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
IIC_iALUi, opc, "\t$Rd, $Rn, $imm", IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
Requires<[IsThumb2]> { Requires<[IsThumb2]> {
@@ -454,7 +506,7 @@ multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, ".w\t$Rd, $Rn, $Rm", opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
Requires<[IsThumb2]> { Requires<[IsThumb2]> {
@@ -468,7 +520,7 @@ multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2TwoRegShiftedReg< def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
@@ -485,7 +537,7 @@ let Defs = [CPSR] in {
multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2TwoRegShiftedImm< def ri : T2sTwoRegImm<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
opc, "\t$Rd, $Rn, $imm", opc, "\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
@@ -497,7 +549,7 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
let Inst{15} = 0; let Inst{15} = 0;
} }
// register // register
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
opc, ".w\t$Rd, $Rn, $Rm", opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
Requires<[IsThumb2]> { Requires<[IsThumb2]> {
@@ -511,7 +563,7 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
let Inst{5-4} = 0b00; // type let Inst{5-4} = 0b00; // type
} }
// shifted register // shifted register
def rs : T2TwoRegShiftedReg< def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
@@ -530,9 +582,10 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
let Defs = [CPSR] in { let Defs = [CPSR] in {
multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, def ri : T2TwoRegImm<
!strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs", (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
[(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -540,9 +593,10 @@ multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
let Inst{15} = 0; let Inst{15} = 0;
} }
// shifted register // shifted register
def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, def rs : T2TwoRegShiftedReg<
!strconcat(opc, "s"), "\t$dst, $rhs, $lhs", (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
[(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = opcod; let Inst{24-21} = opcod;