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Fix the JIT encoding of LWA, LD, STD, and STDU.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-18 16:51:22 +00:00
parent 076866c50f
commit 841d12d9ac
3 changed files with 20 additions and 4 deletions
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4
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -117,6 +117,10 @@ namespace {
MVT::ValueType VT) { MVT::ValueType VT) {
O << (unsigned short)MI->getOperand(OpNo).getImmedValue(); O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
} }
void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
O << (short)MI->getOperand(OpNo).getImmedValue()*4;
}
void printBranchOperand(const MachineInstr *MI, unsigned OpNo, void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) { MVT::ValueType VT) {
// Branches can take an immediate operand. This is used by the branch // Branches can take an immediate operand. This is used by the branch

11
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -89,6 +89,9 @@ def s16imm : Operand<i32> {
def u16imm : Operand<i32> { def u16imm : Operand<i32> {
let PrintMethod = "printU16ImmOperand"; let PrintMethod = "printU16ImmOperand";
} }
def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
let PrintMethod = "printS16X4ImmOperand";
}
def target : Operand<i32> { def target : Operand<i32> {
let PrintMethod = "printBranchOperand"; let PrintMethod = "printBranchOperand";
} }
@ -282,15 +285,15 @@ def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
// DS-Form instructions. Load/Store instructions available in PPC-64 // DS-Form instructions. Load/Store instructions available in PPC-64
// //
let isLoad = 1 in { let isLoad = 1 in {
def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
"lwa $rT, $DS($rA)">, isPPC64; "lwa $rT, $DS($rA)">, isPPC64;
def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
"ld $rT, $DS($rA)">, isPPC64; "ld $rT, $DS($rA)">, isPPC64;
} }
let isStore = 1 in { let isStore = 1 in {
def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
"std $rT, $DS($rA)">, isPPC64; "std $rT, $DS($rA)">, isPPC64;
def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA), def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
"stdu $rT, $DS($rA)">, isPPC64; "stdu $rT, $DS($rA)">, isPPC64;
} }

9
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -271,6 +271,15 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
MI.SetMachineOperandReg(2, PPC::R0); MI.SetMachineOperandReg(2, PPC::R0);
} else { } else {
switch (MI.getOpcode()) {
case PPC::LWA:
case PPC::LD:
case PPC::STD:
case PPC::STDU:
assert((Offset & 3) == 0 && "Invalid frame offset!");
Offset >>= 2; // The actual encoded value has the low two bits zero.
break;
}
MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
Offset); Offset);
} }