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Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing
case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -221,6 +221,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FFLOOR:
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case ISD::FP_ROUND:
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case ISD::FMA:
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case ISD::SIGN_EXTEND_INREG:
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QueryType = Node->getValueType(0);
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@ -544,6 +544,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
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setTargetDAGCombine(ISD::INTRINSIC_VOID);
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setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
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setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
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9
test/CodeGen/ARM/neon_fpconv.ll
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9
test/CodeGen/ARM/neon_fpconv.ll
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@ -0,0 +1,9 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
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define <2 x float> @vtrunc(<2 x double> %a) {
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; CHECK: vcvt.f32.f64 [[S0:s[0-9]+]], [[D0:d[0-9]+]]
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; CHECK: vcvt.f32.f64 [[S1:s[0-9]+]], [[D1:d[0-9]+]]
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%vt = fptrunc <2 x double> %a to <2 x float>
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ret <2 x float> %vt
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}
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