Rename SSARegMap -> MachineRegisterInfo in keeping with the idea

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/AsmPrinter.h

@@ -29,7 +29,7 @@ namespace llvm {
   class MachineConstantPoolValue;
   class Mangler;
   class TargetAsmInfo;
-  
+  class Type;
 
   /// AsmPrinter - This class is intended to be used as a driving class for all
   /// asm writers.

include/llvm/CodeGen/LiveIntervalAnalysis.h

@@ -34,7 +34,7 @@ namespace llvm {
   class LiveVariables;
   class MachineLoopInfo;
   class MRegisterInfo;
-  class SSARegMap;
+  class MachineRegisterInfo;
   class TargetInstrInfo;
   class TargetRegisterClass;
   class VirtRegMap;
@@ -308,18 +308,20 @@ namespace llvm {
 
     bool alsoFoldARestore(int Id, int index, unsigned vr,
                           BitVector &RestoreMBBs,
-                          std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes);
+                          std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
     void eraseRestoreInfo(int Id, int index, unsigned vr,
                           BitVector &RestoreMBBs,
-                          std::map<unsigned,std::vector<SRInfo> > &RestoreIdxes);
+                          std::map<unsigned,std::vector<SRInfo> >&RestoreIdxes);
 
-    /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper functions
-    /// for addIntervalsForSpills to rewrite uses / defs for the given live range.
+    /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
+    /// functions for addIntervalsForSpills to rewrite uses / defs for the given
+    /// live range.
     bool rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
         unsigned id, unsigned index, unsigned end, MachineInstr *MI,
         MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
         bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
-        VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
+        VirtRegMap &vrm, MachineRegisterInfo &RegMap, 
+                                     const TargetRegisterClass* rc,
         SmallVector<int, 4> &ReMatIds,
         unsigned &NewVReg, bool &HasDef, bool &HasUse,
         const MachineLoopInfo *loopInfo,
@@ -329,7 +331,8 @@ namespace llvm {
         LiveInterval::Ranges::const_iterator &I,
         MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
         bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
-        VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
+        VirtRegMap &vrm, MachineRegisterInfo &RegMap,
+                                      const TargetRegisterClass* rc,
         SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
         BitVector &SpillMBBs,
         std::map<unsigned,std::vector<SRInfo> > &SpillIdxes,

include/llvm/CodeGen/MachineFunction.h

@@ -18,16 +18,14 @@
 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
 #define LLVM_CODEGEN_MACHINEFUNCTION_H
 
-#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/Annotation.h"
-#include "llvm/ADT/BitVector.h"
 
 namespace llvm {
 
 class Function;
 class TargetMachine;
-class SSARegMap;
+class MachineRegisterInfo;
 class MachineFrameInfo;
 class MachineConstantPool;
 class MachineJumpTableInfo;
@@ -83,8 +81,8 @@ class MachineFunction : private Annotation {
   // List of machine basic blocks in function
   ilist<MachineBasicBlock> BasicBlocks;
 
-  // Keeping track of mapping from SSA values to registers
-  SSARegMap *SSARegMapping;
+  // RegInfo - Information about each register in use in the function.
+  MachineRegisterInfo *RegInfo;
 
   // Used to keep track of target-specific per-machine function information for
   // the target implementation.
@@ -104,21 +102,6 @@ class MachineFunction : private Annotation {
   // numbered and this vector keeps track of the mapping from ID's to MBB's.
   std::vector<MachineBasicBlock*> MBBNumbering;
 
-  /// UsedPhysRegs - This is a bit vector that is computed and set by the
-  /// register allocator, and must be kept up to date by passes that run after
-  /// register allocation (though most don't modify this).  This is used
-  /// so that the code generator knows which callee save registers to save and
-  /// for other target specific uses.
-  BitVector UsedPhysRegs;
-
-  /// LiveIns/LiveOuts - Keep track of the physical registers that are
-  /// livein/liveout of the function.  Live in values are typically arguments in
-  /// registers, live out values are typically return values in registers.
-  /// LiveIn values are allowed to have virtual registers associated with them,
-  /// stored in the second element.
-  std::vector<std::pair<unsigned, unsigned> > LiveIns;
-  std::vector<unsigned> LiveOuts;
-  
 public:
   MachineFunction(const Function *Fn, const TargetMachine &TM);
   ~MachineFunction();
@@ -131,11 +114,9 @@ public:
   ///
   const TargetMachine &getTarget() const { return Target; }
 
-  /// SSARegMap Interface... Keep track of information about each SSA virtual
-  /// register, such as which register class it belongs to.
+  /// getRegInfo - Return information about the registers currently in use.
   ///
-  SSARegMap *getSSARegMap() const { return SSARegMapping; }
-  void clearSSARegMap();
+  MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
 
   /// getFrameInfo - Return the frame info object for the current function.
   /// This object contains information about objects allocated on the stack
@@ -171,39 +152,6 @@ public:
      return const_cast<MachineFunction*>(this)->getInfo<Ty>();
   }
 
-  /// isPhysRegUsed - Return true if the specified register is used in this
-  /// function.  This only works after register allocation.
-  bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
-
-  /// setPhysRegUsed - Mark the specified register used in this function.
-  /// This should only be called during and after register allocation.
-  void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
-
-  /// setPhysRegUnused - Mark the specified register unused in this function.
-  /// This should only be called during and after register allocation.
-  void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
-
-  // LiveIn/LiveOut management methods.
-
-  /// addLiveIn/Out - Add the specified register as a live in/out.  Note that it
-  /// is an error to add the same register to the same set more than once.
-  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
-    LiveIns.push_back(std::make_pair(Reg, vreg));
-  }
-  void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
-
-  // Iteration support for live in/out sets.  These sets are kept in sorted
-  // order by their register number.
-  typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
-  livein_iterator;
-  typedef std::vector<unsigned>::const_iterator liveout_iterator;
-  livein_iterator livein_begin() const { return LiveIns.begin(); }
-  livein_iterator livein_end()   const { return LiveIns.end(); }
-  bool            livein_empty() const { return LiveIns.empty(); }
-  liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
-  liveout_iterator liveout_end()   const { return LiveOuts.end(); }
-  bool             liveout_empty() const { return LiveOuts.empty(); }
-
   /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they
   /// are inserted into the machine function.  The block number for a machine
   /// basic block can be found by using the MBB::getBlockNumber method, this

include/llvm/CodeGen/MachineRegisterInfo.h

@@ -0,0 +1,118 @@
+//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MachineRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
+#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
+
+#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/ADT/BitVector.h"
+#include <vector>
+
+namespace llvm {
+  
+/// MachineRegisterInfo - Keep track of information for each virtual register,
+/// including its register class.
+class MachineRegisterInfo {
+  /// VRegInfo - Information we keep for each virtual register.  The entries in
+  /// this vector are actually converted to vreg numbers by adding the 
+  /// MRegisterInfo::FirstVirtualRegister delta to their index.
+  std::vector<const TargetRegisterClass*> VRegInfo;
+  
+  /// UsedPhysRegs - This is a bit vector that is computed and set by the
+  /// register allocator, and must be kept up to date by passes that run after
+  /// register allocation (though most don't modify this).  This is used
+  /// so that the code generator knows which callee save registers to save and
+  /// for other target specific uses.
+  BitVector UsedPhysRegs;
+  
+  /// LiveIns/LiveOuts - Keep track of the physical registers that are
+  /// livein/liveout of the function.  Live in values are typically arguments in
+  /// registers, live out values are typically return values in registers.
+  /// LiveIn values are allowed to have virtual registers associated with them,
+  /// stored in the second element.
+  std::vector<std::pair<unsigned, unsigned> > LiveIns;
+  std::vector<unsigned> LiveOuts;
+public:
+  MachineRegisterInfo(const MRegisterInfo &MRI);
+  
+  
+  //===--------------------------------------------------------------------===//
+  // Virtual Register Info
+  //===--------------------------------------------------------------------===//
+  
+  /// getRegClass - Return the register class of the specified virtual register.
+  const TargetRegisterClass *getRegClass(unsigned Reg) {
+    Reg -= MRegisterInfo::FirstVirtualRegister;
+    assert(Reg < VRegInfo.size() && "Invalid vreg!");
+    return VRegInfo[Reg];
+  }
+
+  /// createVirtualRegister - Create and return a new virtual register in the
+  /// function with the specified register class.
+  ///
+  unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
+    assert(RegClass && "Cannot create register without RegClass!");
+    VRegInfo.push_back(RegClass);
+    return getLastVirtReg();
+  }
+
+  /// getLastVirtReg - Return the highest currently assigned virtual register.
+  ///
+  unsigned getLastVirtReg() const {
+    return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
+  }
+  
+  //===--------------------------------------------------------------------===//
+  // Physical Register Use Info
+  //===--------------------------------------------------------------------===//
+  
+  /// isPhysRegUsed - Return true if the specified register is used in this
+  /// function.  This only works after register allocation.
+  bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
+  
+  /// setPhysRegUsed - Mark the specified register used in this function.
+  /// This should only be called during and after register allocation.
+  void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
+  
+  /// setPhysRegUnused - Mark the specified register unused in this function.
+  /// This should only be called during and after register allocation.
+  void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
+  
+
+  //===--------------------------------------------------------------------===//
+  // LiveIn/LiveOut Management
+  //===--------------------------------------------------------------------===//
+  
+  /// addLiveIn/Out - Add the specified register as a live in/out.  Note that it
+  /// is an error to add the same register to the same set more than once.
+  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
+    LiveIns.push_back(std::make_pair(Reg, vreg));
+  }
+  void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
+  
+  // Iteration support for live in/out sets.  These sets are kept in sorted
+  // order by their register number.
+  typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
+  livein_iterator;
+  typedef std::vector<unsigned>::const_iterator liveout_iterator;
+  livein_iterator livein_begin() const { return LiveIns.begin(); }
+  livein_iterator livein_end()   const { return LiveIns.end(); }
+  bool            livein_empty() const { return LiveIns.empty(); }
+  liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
+  liveout_iterator liveout_end()   const { return LiveOuts.end(); }
+  bool             liveout_empty() const { return LiveOuts.empty(); }
+};
+
+} // End llvm namespace
+
+#endif

include/llvm/CodeGen/SSARegMap.h

@@ -1,60 +0,0 @@
-//===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the SSARegMap class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_SSAREGMAP_H
-#define LLVM_CODEGEN_SSAREGMAP_H
-
-#include "llvm/Target/MRegisterInfo.h"
-#include <vector>
-
-namespace llvm {
-  
-/// SSARegMap - Keep track of information for each virtual register, including
-/// its register class.
-class SSARegMap {
-  /// VRegInfo - Information we keep for each virtual register.  The entries in
-  /// this vector are actually converted to vreg numbers by adding the 
-  /// MRegisterInfo::FirstVirtualRegister delta to their index.
-  std::vector<const TargetRegisterClass*> VRegInfo;
-  
-public:
-  SSARegMap() {
-    VRegInfo.reserve(256);
-  }
-
-  /// getRegClass - Return the register class of the specified virtual register.
-  const TargetRegisterClass *getRegClass(unsigned Reg) {
-    Reg -= MRegisterInfo::FirstVirtualRegister;
-    assert(Reg < VRegInfo.size() && "Invalid vreg!");
-    return VRegInfo[Reg];
-  }
-
-  /// createVirtualRegister - Create and return a new virtual register in the
-  /// function with the specified register class.
-  ///
-  unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
-    assert(RegClass && "Cannot create register without RegClass!");
-    VRegInfo.push_back(RegClass);
-    return getLastVirtReg();
-  }
-
-  /// getLastVirtReg - Return the highest currently assigned virtual register.
-  ///
-  unsigned getLastVirtReg() const {
-    return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
-  }
-};
-
-} // End llvm namespace
-
-#endif

include/llvm/CodeGen/ScheduleDAG.h

@@ -25,11 +25,11 @@ namespace llvm {
   struct SUnit;
   class MachineConstantPool;
   class MachineModuleInfo;
+  class MachineRegisterInfo;
   class MachineInstr;
   class MRegisterInfo;
   class SelectionDAG;
   class SelectionDAGISel;
-  class SSARegMap;
   class TargetInstrInfo;
   class TargetInstrDescriptor;
   class TargetMachine;
@@ -243,7 +243,7 @@ namespace llvm {
     const TargetMachine &TM;              // Target processor
     const TargetInstrInfo *TII;           // Target instruction information
     const MRegisterInfo *MRI;             // Target processor register info
-    SSARegMap *RegMap;                    // Virtual/real register map
+    MachineRegisterInfo &RegInfo;         // Virtual/real register map
     MachineConstantPool *ConstPool;       // Target constant pool
     std::vector<SUnit*> Sequence;         // The schedule. Null SUnit*'s
                                           // represent noop instructions.
@@ -253,8 +253,7 @@ namespace llvm {
     SmallSet<SDNode*, 16> CommuteSet;     // Nodes the should be commuted.
 
     ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
-                const TargetMachine &tm)
-      : DAG(dag), BB(bb), TM(tm) {}
+                const TargetMachine &tm);
 
     virtual ~ScheduleDAG() {}
 

include/llvm/CodeGen/SelectionDAGISel.h

@@ -23,7 +23,7 @@
 namespace llvm {
   class SelectionDAGLowering;
   class SDOperand;
-  class SSARegMap;
+  class MachineRegisterInfo;
   class MachineBasicBlock;
   class MachineFunction;
   class MachineInstr;
@@ -36,7 +36,7 @@ namespace llvm {
 class SelectionDAGISel : public FunctionPass {
 public:
   TargetLowering &TLI;
-  SSARegMap *RegMap;
+  MachineRegisterInfo *RegInfo;
   SelectionDAG *CurDAG;
   MachineBasicBlock *BB;
   AliasAnalysis *AA;