mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-16 11:24:39 +00:00
ARM VST1 single lane assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
@@ -4751,7 +4751,61 @@ validateInstruction(MCInst &Inst,
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return false;
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}
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static unsigned getRealVLDNOpcode(unsigned Opc) {
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static unsigned getRealVSTLNOpcode(unsigned Opc) {
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switch(Opc) {
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default: assert(0 && "unexpected opcode!");
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case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD;
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case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD;
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case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD;
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case ARM::VST1LNdAsm_8: return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8;
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case ARM::VST1LNdAsm_16: return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16;
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case ARM::VST1LNdAsm_32: return ARM::VST1LNd32;
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case ARM::VST1LNdAsm_F: return ARM::VST1LNd32;
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case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32;
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case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32;
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case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32;
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case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32;
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}
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}
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static unsigned getRealVLDLNOpcode(unsigned Opc) {
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switch(Opc) {
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default: assert(0 && "unexpected opcode!");
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case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
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@@ -4809,6 +4863,98 @@ bool ARMAsmParser::
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processInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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// Handle NEON VST1 complex aliases.
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case ARM::VST1LNdWB_register_Asm_8:
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case ARM::VST1LNdWB_register_Asm_P8:
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case ARM::VST1LNdWB_register_Asm_I8:
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case ARM::VST1LNdWB_register_Asm_S8:
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case ARM::VST1LNdWB_register_Asm_U8:
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case ARM::VST1LNdWB_register_Asm_16:
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case ARM::VST1LNdWB_register_Asm_P16:
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case ARM::VST1LNdWB_register_Asm_I16:
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case ARM::VST1LNdWB_register_Asm_S16:
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case ARM::VST1LNdWB_register_Asm_U16:
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case ARM::VST1LNdWB_register_Asm_32:
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case ARM::VST1LNdWB_register_Asm_F:
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case ARM::VST1LNdWB_register_Asm_F32:
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case ARM::VST1LNdWB_register_Asm_I32:
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case ARM::VST1LNdWB_register_Asm_S32:
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case ARM::VST1LNdWB_register_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(4)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST1LNdWB_fixed_Asm_8:
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case ARM::VST1LNdWB_fixed_Asm_P8:
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case ARM::VST1LNdWB_fixed_Asm_I8:
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case ARM::VST1LNdWB_fixed_Asm_S8:
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case ARM::VST1LNdWB_fixed_Asm_U8:
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case ARM::VST1LNdWB_fixed_Asm_16:
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case ARM::VST1LNdWB_fixed_Asm_P16:
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case ARM::VST1LNdWB_fixed_Asm_I16:
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case ARM::VST1LNdWB_fixed_Asm_S16:
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case ARM::VST1LNdWB_fixed_Asm_U16:
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case ARM::VST1LNdWB_fixed_Asm_32:
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case ARM::VST1LNdWB_fixed_Asm_F:
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case ARM::VST1LNdWB_fixed_Asm_F32:
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case ARM::VST1LNdWB_fixed_Asm_I32:
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case ARM::VST1LNdWB_fixed_Asm_S32:
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case ARM::VST1LNdWB_fixed_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST1LNdAsm_8:
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case ARM::VST1LNdAsm_P8:
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case ARM::VST1LNdAsm_I8:
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case ARM::VST1LNdAsm_S8:
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case ARM::VST1LNdAsm_U8:
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case ARM::VST1LNdAsm_16:
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case ARM::VST1LNdAsm_P16:
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case ARM::VST1LNdAsm_I16:
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case ARM::VST1LNdAsm_S16:
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case ARM::VST1LNdAsm_U16:
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case ARM::VST1LNdAsm_32:
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case ARM::VST1LNdAsm_F:
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case ARM::VST1LNdAsm_F32:
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case ARM::VST1LNdAsm_I32:
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case ARM::VST1LNdAsm_S32:
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case ARM::VST1LNdAsm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// Handle NEON VLD1 complex aliases.
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case ARM::VLD1LNdWB_register_Asm_8:
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case ARM::VLD1LNdWB_register_Asm_P8:
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@@ -4829,7 +4975,7 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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@@ -4861,7 +5007,7 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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@@ -4893,7 +5039,7 @@ processInstruction(MCInst &Inst,
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
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TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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