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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-10 08:40:41 +00:00
Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
14f1d4e74b
commit
852a7e362e
@ -33,6 +33,7 @@
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -1183,11 +1184,8 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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// FIXME: For now require that the destination subregs match the subregs
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// being extracted.
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if (!UseMI->isExtractSubreg() ||
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UseMI->getOperand(0).getReg() != DstReg ||
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UseMI->getOperand(0).getSubReg() != UseMI->getOperand(2).getImm() ||
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UseMI->getOperand(1).getSubReg() != 0) {
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CanCoalesce = false;
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break;
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@ -1198,40 +1196,92 @@ TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
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if (!CanCoalesce || SubIndices.size() < 2)
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continue;
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// FIXME: For now require that the src and dst registers are in the
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// same regclass.
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if (MRI->getRegClass(SrcReg) != MRI->getRegClass(DstReg))
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std::sort(SubIndices.begin(), SubIndices.end());
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unsigned NewSrcSubIdx = 0;
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if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices,
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NewSrcSubIdx))
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continue;
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std::sort(SubIndices.begin(), SubIndices.end());
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unsigned NewSubIdx = 0;
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if (TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices,
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NewSubIdx)) {
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bool Proceed = true;
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if (NewSubIdx)
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for (MachineRegisterInfo::reg_nodbg_iterator
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RI = MRI->reg_nodbg_begin(SrcReg), RE = MRI->reg_nodbg_end();
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RI != RE; ) {
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MachineOperand &MO = RI.getOperand();
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++RI;
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// FIXME: If the sub-registers do not combine to the whole
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// super-register, i.e. NewSubIdx != 0, and any of the use has a
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// sub-register index, then abort the coalescing attempt.
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if (MO.getSubReg()) {
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Proceed = false;
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break;
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}
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}
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if (Proceed)
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for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
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RE = MRI->reg_end(); RI != RE; ) {
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MachineOperand &MO = RI.getOperand();
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++RI;
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MO.setReg(DstReg);
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if (NewSubIdx)
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MO.setSubReg(NewSubIdx);
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}
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// Now that we know that all the uses are extract_subregs and that those
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// subregs can somehow be combined, scan all the extract_subregs again to
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// make sure the subregs are in the right order and can be composed.
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// Also keep track of the destination subregisters so we can make sure
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// that those can be combined.
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SubIndices.clear();
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MachineInstr *SomeMI = 0;
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CanCoalesce = true;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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assert(UseMI->isExtractSubreg());
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unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
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unsigned SrcSubIdx = UseMI->getOperand(2).getImm();
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assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
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if (TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) {
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CanCoalesce = false;
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break;
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}
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SubIndices.push_back(DstSubIdx);
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// Keep track of one of the uses.
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SomeMI = UseMI;
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}
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if (!CanCoalesce)
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continue;
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// Check that the destination subregisters can also be combined.
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std::sort(SubIndices.begin(), SubIndices.end());
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unsigned NewDstSubIdx = 0;
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if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), SubIndices,
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NewDstSubIdx))
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continue;
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// If neither source nor destination can be combined to the full register,
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// just give up. This could be improved if it ever matters.
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if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
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continue;
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// Insert a copy or an extract to replace the original extracts.
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MachineBasicBlock::iterator InsertLoc = SomeMI;
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if (NewSrcSubIdx) {
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// Insert an extract subreg.
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BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
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TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg)
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.addReg(SrcReg).addImm(NewSrcSubIdx);
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} else if (NewDstSubIdx) {
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// Do a subreg insertion.
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BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
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TII->get(TargetOpcode::INSERT_SUBREG), DstReg)
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.addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx);
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} else {
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// Insert a copy.
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bool Emitted =
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TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg,
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MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg),
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SomeMI->getDebugLoc());
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(void)Emitted;
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}
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MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
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// Remove all the old extract instructions.
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ) {
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MachineInstr *UseMI = &*UI;
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++UI;
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if (UseMI == CopyMI)
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continue;
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assert(UseMI->isExtractSubreg());
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// Move any kills to the new copy or extract instruction.
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if (UseMI->getOperand(1).isKill()) {
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MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg);
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KillMO->setIsKill();
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if (LV)
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// Update live variables
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LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
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}
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UseMI->eraseFromParent();
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}
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}
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}
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@ -11,11 +11,11 @@ entry:
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%0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
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store <4 x float> %quat.0, <4 x float>* %0
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%1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
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;CHECK: vmov.f32
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;CHECK: vmov.f32
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%2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2]
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%3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
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%4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
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;CHECK-NOT: vmov
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;CHECK: vpadd
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%5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2]
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%6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2]
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%7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2]
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