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StructurizeCFG: Use LoopInfo analysis for better loop detection

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We were assuming that each back-edge in a region represented a unique
loop, which is not always the case.  We need to use LoopInfo to
correctly determine which back-edges are loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-12-03 04:28:32 +00:00
parent 2212800542
commit 857550322c
2 changed files with 47 additions and 1 deletions
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7
lib/Transforms/Scalar/StructurizeCFG.cpp
View File

@ -10,6 +10,7 @@
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include "llvm/ADT/MapVector.h" #include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SCCIterator.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/RegionInfo.h" #include "llvm/Analysis/RegionInfo.h"
#include "llvm/Analysis/RegionIterator.h" #include "llvm/Analysis/RegionIterator.h"
#include "llvm/Analysis/RegionPass.h" #include "llvm/Analysis/RegionPass.h"
@ -166,6 +167,7 @@ class StructurizeCFG : public RegionPass {
Region *ParentRegion; Region *ParentRegion;
DominatorTree *DT; DominatorTree *DT;
LoopInfo *LI;
RNVector Order; RNVector Order;
BBSet Visited; BBSet Visited;
@ -247,6 +249,7 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequiredID(LowerSwitchID); AU.addRequiredID(LowerSwitchID);
AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<LoopInfo>();
AU.addPreserved<DominatorTreeWrapperPass>(); AU.addPreserved<DominatorTreeWrapperPass>();
RegionPass::getAnalysisUsage(AU); RegionPass::getAnalysisUsage(AU);
} }
@ -301,11 +304,12 @@ void StructurizeCFG::analyzeLoops(RegionNode *N) {
for (unsigned i = 0, e = Term->getNumSuccessors(); i != e; ++i) { for (unsigned i = 0, e = Term->getNumSuccessors(); i != e; ++i) {
BasicBlock *Succ = Term->getSuccessor(i); BasicBlock *Succ = Term->getSuccessor(i);
if (Visited.count(Succ)) if (Visited.count(Succ) && LI->isLoopHeader(Succ) ) {
Loops[Succ] = BB; Loops[Succ] = BB;
} }
} }
} }
}
/// \brief Invert the given condition /// \brief Invert the given condition
Value *StructurizeCFG::invert(Value *Condition) { Value *StructurizeCFG::invert(Value *Condition) {
@ -862,6 +866,7 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassManager &RGM) {
ParentRegion = R; ParentRegion = R;
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree(); DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
LI = &getAnalysis<LoopInfo>();
orderNodes(); orderNodes();
collectInfos(); collectInfos();

41
test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll Normal file
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@ -0,0 +1,41 @@
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
; CHECK-NOT: br i1 true
define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) {
; CHECK: bb:
bb:
br label %bb3
; CHECK: bb3:
bb3: ; preds = %bb7, %bb
%tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
%tmp4 = fcmp ult float %arg1, 3.500000e+00
; CHECK: br i1 %tmp4, label %bb7, label %Flow
br i1 %tmp4, label %bb7, label %bb5
; CHECK: Flow:
; CHECK: br i1 %2, label %Flow1, label %bb3
; CHECK: Flow1:
; CHECK: br i1 %3, label %bb5, label %bb10
; CHECK: bb5:
bb5: ; preds = %bb3
%tmp6 = fcmp olt float 0.000000e+00, %arg2
; CHECK: br label %bb10
br i1 %tmp6, label %bb10, label %bb7
; CHECK: bb7
bb7: ; preds = %bb5, %bb3
%tmp8 = add nuw nsw i64 %tmp, 1
%tmp9 = icmp slt i64 %tmp8, 5
; CHECK: br label %Flow
br i1 %tmp9, label %bb3, label %bb10
; CHECK: bb10
bb10: ; preds = %bb7, %bb5
%tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
store i32 %tmp11, i32 addrspace(1)* %arg, align 4
ret void
}