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https://github.com/c64scene-ar/llvm-6502.git
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Rewrite branches more closely to correct. This makes more stuff pass, and
stops the infinite loops! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18194 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -33,8 +33,7 @@ namespace {
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void *MovePCtoLROffset;
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void *MovePCtoLROffset;
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// Tracks which instruction references which BasicBlock
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// Tracks which instruction references which BasicBlock
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std::vector<std::pair<const BasicBlock*,
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std::vector<std::pair<const BasicBlock*, unsigned*> > BBRefs;
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std::pair<unsigned*,MachineInstr*> > > BBRefs;
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// Tracks where each BasicBlock starts
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// Tracks where each BasicBlock starts
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std::map<const BasicBlock*, long> BBLocations;
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std::map<const BasicBlock*, long> BBLocations;
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@@ -98,24 +97,20 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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// Resolve branches to BasicBlocks for the entire function
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// Resolve branches to BasicBlocks for the entire function
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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intptr_t Location = BBLocations[BBRefs[i].first];
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intptr_t Location = BBLocations[BBRefs[i].first];
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unsigned *Ref = BBRefs[i].second.first;
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unsigned *Ref = BBRefs[i].second;
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MachineInstr *MI = BBRefs[i].second.second;
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DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
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DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
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<< " in instr: " << *MI);
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<< "\n");
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for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
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unsigned Instr = *Ref;
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MachineOperand &op = MI->getOperand(ii);
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intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
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if (op.isPCRelativeDisp()) {
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// the instruction's branch target is made such that it branches to
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switch (Instr >> 26) {
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// PC + (branchTarget * 4), so undo that arithmetic here:
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default: assert(0 && "Unknown branch user!");
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// Location is the target of the branch
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case 18: // This is B or BL
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// Ref is the location of the instruction, and hence the PC
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*Ref |= (BranchTargetDisp & ((1 << 24)-1)) << 2;
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int64_t branchTarget = (Location - (long)Ref) >> 2;
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break;
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MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
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case 16: // This is BLT,BLE,BEQ,BGE,BGT,BNE, or other bcx instruction
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branchTarget);
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*Ref |= (BranchTargetDisp & ((1 << 14)-1)) << 2;
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unsigned fixedInstr = PPC32CodeEmitter::getBinaryCodeForInstr(*MI);
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break;
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MCE.emitWordAt(fixedInstr, Ref);
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break;
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}
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}
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}
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}
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}
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BBRefs.clear();
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BBRefs.clear();
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@@ -210,7 +205,7 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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} else if (MO.isMachineBasicBlock()) {
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} else if (MO.isMachineBasicBlock()) {
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const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
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const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
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BBRefs.push_back(std::make_pair(BB, CurrPC));
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} else if (MO.isConstantPoolIndex()) {
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} else if (MO.isConstantPoolIndex()) {
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unsigned index = MO.getConstantPoolIndex();
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unsigned index = MO.getConstantPoolIndex();
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rv = MCE.getConstantPoolEntryAddress(index);
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rv = MCE.getConstantPoolEntryAddress(index);
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