Rewrite branches more closely to correct. This makes more stuff pass, and

stops the infinite loops!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-11-24 01:35:12 +00:00
parent 310a752872
commit 8599d385a2

View File

@@ -33,8 +33,7 @@ namespace {
void *MovePCtoLROffset; void *MovePCtoLROffset;
// Tracks which instruction references which BasicBlock // Tracks which instruction references which BasicBlock
std::vector<std::pair<const BasicBlock*, std::vector<std::pair<const BasicBlock*, unsigned*> > BBRefs;
std::pair<unsigned*,MachineInstr*> > > BBRefs;
// Tracks where each BasicBlock starts // Tracks where each BasicBlock starts
std::map<const BasicBlock*, long> BBLocations; std::map<const BasicBlock*, long> BBLocations;
@@ -98,24 +97,20 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
// Resolve branches to BasicBlocks for the entire function // Resolve branches to BasicBlocks for the entire function
for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
intptr_t Location = BBLocations[BBRefs[i].first]; intptr_t Location = BBLocations[BBRefs[i].first];
unsigned *Ref = BBRefs[i].second.first; unsigned *Ref = BBRefs[i].second;
MachineInstr *MI = BBRefs[i].second.second;
DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location
<< " in instr: " << *MI); << "\n");
for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) { unsigned Instr = *Ref;
MachineOperand &op = MI->getOperand(ii); intptr_t BranchTargetDisp = (Location - (intptr_t)Ref) >> 2;
if (op.isPCRelativeDisp()) {
// the instruction's branch target is made such that it branches to switch (Instr >> 26) {
// PC + (branchTarget * 4), so undo that arithmetic here: default: assert(0 && "Unknown branch user!");
// Location is the target of the branch case 18: // This is B or BL
// Ref is the location of the instruction, and hence the PC *Ref |= (BranchTargetDisp & ((1 << 24)-1)) << 2;
int64_t branchTarget = (Location - (long)Ref) >> 2; break;
MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed, case 16: // This is BLT,BLE,BEQ,BGE,BGT,BNE, or other bcx instruction
branchTarget); *Ref |= (BranchTargetDisp & ((1 << 14)-1)) << 2;
unsigned fixedInstr = PPC32CodeEmitter::getBinaryCodeForInstr(*MI); break;
MCE.emitWordAt(fixedInstr, Ref);
break;
}
} }
} }
BBRefs.clear(); BBRefs.clear();
@@ -210,7 +205,7 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
} else if (MO.isMachineBasicBlock()) { } else if (MO.isMachineBasicBlock()) {
const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock(); const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue(); unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI))); BBRefs.push_back(std::make_pair(BB, CurrPC));
} else if (MO.isConstantPoolIndex()) { } else if (MO.isConstantPoolIndex()) {
unsigned index = MO.getConstantPoolIndex(); unsigned index = MO.getConstantPoolIndex();
rv = MCE.getConstantPoolEntryAddress(index); rv = MCE.getConstantPoolEntryAddress(index);