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Add "write back" bit encoding.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2010-11-08 21:28:03 +00:00
parent a84ad90c06
commit 85c3f24da3
1 changed files with 16 additions and 8 deletions
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24
lib/Target/ARM/ARMInstrVFP.td
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@@ -80,14 +80,16 @@ def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeNone, IIC_fpLoad_m, IndexModeNone, IIC_fpLoad_m,
"vldm${amode}${p}\t$Rn, $dsts", "", []> { "vldm${amode}${p}\t$Rn, $dsts", "", []> {
let Inst{20} = 1; let Inst{21} = 0; // wback = (W == '1')
let Inst{20} = 1; // Load
} }
def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeNone, IIC_fpLoad_m, IndexModeNone, IIC_fpLoad_m,
"vldm${amode}${p}\t$Rn, $dsts", "", []> { "vldm${amode}${p}\t$Rn, $dsts", "", []> {
let Inst{20} = 1; let Inst{21} = 0; // wback = (W == '1')
let Inst{20} = 1; // Load
} }
def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -95,7 +97,8 @@ def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
IndexModeUpd, IIC_fpLoad_mu, IndexModeUpd, IIC_fpLoad_mu,
"vldm${amode}${p}\t$Rn!, $dsts", "vldm${amode}${p}\t$Rn!, $dsts",
"$Rn = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 1; let Inst{21} = 1; // wback = (W == '1')
let Inst{20} = 1; // Load
} }
def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -103,7 +106,8 @@ def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
IndexModeUpd, IIC_fpLoad_mu, IndexModeUpd, IIC_fpLoad_mu,
"vldm${amode}${p}\t$Rn!, $dsts", "vldm${amode}${p}\t$Rn!, $dsts",
"$Rn = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 1; let Inst{21} = 1; // wback = (W == '1')
let Inst{20} = 1; // Load
} }
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
@@ -113,14 +117,16 @@ def VSTMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), reglist:$srcs, variable_ops),
IndexModeNone, IIC_fpStore_m, IndexModeNone, IIC_fpStore_m,
"vstm${amode}${p}\t$Rn, $srcs", "", []> { "vstm${amode}${p}\t$Rn, $srcs", "", []> {
let Inst{20} = 0; let Inst{21} = 0; // wback = (W == '1')
let Inst{20} = 0; // Store
} }
def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$srcs, variable_ops), IndexModeNone, reglist:$srcs, variable_ops), IndexModeNone,
IIC_fpStore_m, IIC_fpStore_m,
"vstm${amode}${p}\t$Rn, $srcs", "", []> { "vstm${amode}${p}\t$Rn, $srcs", "", []> {
let Inst{20} = 0; let Inst{21} = 0; // wback = (W == '1')
let Inst{20} = 0; // Store
} }
def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -128,7 +134,8 @@ def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
IndexModeUpd, IIC_fpStore_mu, IndexModeUpd, IIC_fpStore_mu,
"vstm${amode}${p}\t$Rn!, $srcs", "vstm${amode}${p}\t$Rn!, $srcs",
"$Rn = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 0; let Inst{21} = 1; // wback = (W == '1')
let Inst{20} = 0; // Store
} }
def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -136,7 +143,8 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
IndexModeUpd, IIC_fpStore_mu, IndexModeUpd, IIC_fpStore_mu,
"vstm${amode}${p}\t$Rn!, $srcs", "vstm${amode}${p}\t$Rn!, $srcs",
"$Rn = $wb", []> { "$Rn = $wb", []> {
let Inst{20} = 0; let Inst{21} = 1; // wback = (W == '1')
let Inst{20} = 0; // Store
} }
} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq