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Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll:test3

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-10-15 22:18:08 +00:00
parent 34f342e36f
commit 85d63bbff7
1 changed files with 14 additions and 0 deletions
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14
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -803,6 +803,20 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
WorkList.push_back(ANDNode.Val); WorkList.push_back(ANDNode.Val);
return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
} }
// fold (and (sra)) -> (and (srl)) when possible.
if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
// If the RHS of the AND has zeros where the sign bits of the SRA will
// land, turn the SRA into an SRL.
if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
(~0ULL>>(64-OpSizeInBits)), TLI)) {
WorkList.push_back(N);
CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
N0.getOperand(1)));
return SDOperand();
}
}
// fold (zext_inreg (extload x)) -> (zextload x) // fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) { if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();