mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-01 15:17:25 +00:00
R600: Implement getRsqrtEstimate
Only do for f32 since I'm unclear on both what this is expecting for the refinement steps in terms of accuracy, and what f64 instruction actually provides. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225827 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -2567,6 +2567,24 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
}
|
||||
|
||||
SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
|
||||
DAGCombinerInfo &DCI,
|
||||
unsigned &RefinementSteps,
|
||||
bool &UseOneConstNR) const {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
EVT VT = Operand.getValueType();
|
||||
|
||||
if (VT == MVT::f32) {
|
||||
RefinementSteps = 0;
|
||||
return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
|
||||
}
|
||||
|
||||
// TODO: There is also f64 rsq instruction, but the documentation is less
|
||||
// clear on its precision.
|
||||
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static void computeKnownBitsForMinMax(const SDValue Op0,
|
||||
const SDValue Op1,
|
||||
APInt &KnownZero,
|
||||
|
||||
Reference in New Issue
Block a user