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*fixed disassembly of some i386 system insts with intel syntax
*added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -352,11 +352,11 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
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// Descriptor-table support instructions
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def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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"sgdtw\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
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"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
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def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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"sgdt\t$dst", [], IIC_SGDT>, TB;
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def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
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"sidtw\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>;
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"sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>;
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def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
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"sidt\t$dst", []>, TB;
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def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
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@ -374,11 +374,11 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
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"sldt{q}\t$dst", [], IIC_SLDT>, TB;
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def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
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"lgdtw\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>;
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"lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>;
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def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
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"lgdt\t$src", [], IIC_LGDT>, TB;
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def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
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"lidtw\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>;
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"lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>;
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def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
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"lidt\t$src", [], IIC_LIDT>, TB;
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def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
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13
test/MC/Disassembler/X86/intel-syntax-32.txt
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13
test/MC/Disassembler/X86/intel-syntax-32.txt
Normal file
@ -0,0 +1,13 @@
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# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s
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# CHECK: sgdt
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0x0f 0x01 0x00
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# CHECK: sidt
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0x0f 0x01 0x08
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# CHECK: lgdt
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0x0f 0x01 0x10
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# CHECK: lidt
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0x0f 0x01 0x18
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