mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
8232ece5c1
commit
8688a58c53
@ -455,6 +455,9 @@ namespace ISD {
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FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
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FLOG, FLOG2, FLOG10, FEXP, FEXP2,
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FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
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/// FSINCOS - Compute both fsin and fcos as a single operation.
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FSINCOS,
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/// LOAD and STORE have token chains as their first operand, then the same
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/// operands as an LLVM load/store instruction, then an offset node that
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@ -158,6 +158,11 @@ namespace RTLIB {
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COS_F80,
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COS_F128,
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COS_PPCF128,
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SINCOS_F32,
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SINCOS_F64,
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SINCOS_F80,
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SINCOS_F128,
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SINCOS_PPCF128,
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POW_F32,
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POW_F64,
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POW_F80,
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@ -102,7 +102,8 @@ private:
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SDNode *Node, bool isSigned);
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SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
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RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
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RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128);
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RTLIB::Libcall Call_F128,
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RTLIB::Libcall Call_PPCF128);
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SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
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RTLIB::Libcall Call_I8,
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RTLIB::Libcall Call_I16,
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@ -110,6 +111,7 @@ private:
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RTLIB::Libcall Call_I64,
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RTLIB::Libcall Call_I128);
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void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
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SDValue ExpandBUILD_VECTOR(SDNode *Node);
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@ -2095,6 +2097,106 @@ SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
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Results.push_back(Rem);
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}
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/// isSinCosLibcallAvailable - Return true if sincos libcall is available.
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static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unexpected request for libcall!");
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case MVT::f32: LC = RTLIB::SINCOS_F32; break;
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case MVT::f64: LC = RTLIB::SINCOS_F64; break;
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case MVT::f80: LC = RTLIB::SINCOS_F80; break;
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case MVT::f128: LC = RTLIB::SINCOS_F128; break;
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case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
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}
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return TLI.getLibcallName(LC) != 0;
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}
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/// useSinCos - Only issue sincos libcall if both sin and cos are
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/// needed.
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static bool useSinCos(SDNode *Node) {
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unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
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? ISD::FCOS : ISD::FSIN;
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SDValue Op0 = Node->getOperand(0);
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for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
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UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
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SDNode *User = *UI;
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if (User == Node)
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continue;
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// The other user might have been turned into sincos already.
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if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
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return true;
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}
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return false;
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}
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/// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
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/// pairs.
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void
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SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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RTLIB::Libcall LC;
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switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unexpected request for libcall!");
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case MVT::f32: LC = RTLIB::SINCOS_F32; break;
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case MVT::f64: LC = RTLIB::SINCOS_F64; break;
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case MVT::f80: LC = RTLIB::SINCOS_F80; break;
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case MVT::f128: LC = RTLIB::SINCOS_F128; break;
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case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
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}
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// The input chain to this libcall is the entry node of the function.
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// Legalizing the call will automatically add the previous call to the
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// dependence.
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SDValue InChain = DAG.getEntryNode();
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EVT RetVT = Node->getValueType(0);
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Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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// Pass the argument.
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Entry.Node = Node->getOperand(0);
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Entry.Ty = RetTy;
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Entry.isSExt = false;
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Entry.isZExt = false;
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Args.push_back(Entry);
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// Pass the return address of sin.
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SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
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Entry.Node = SinPtr;
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Entry.Ty = RetTy->getPointerTo();
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Entry.isSExt = false;
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Entry.isZExt = false;
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Args.push_back(Entry);
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// Also pass the return address of the cos.
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SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
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Entry.Node = CosPtr;
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Entry.Ty = RetTy->getPointerTo();
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Entry.isSExt = false;
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Entry.isZExt = false;
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Args.push_back(Entry);
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SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
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TLI.getPointerTy());
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DebugLoc dl = Node->getDebugLoc();
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TargetLowering::
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CallLoweringInfo CLI(InChain, Type::getVoidTy(*DAG.getContext()),
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false, false, false, false,
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0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, dl);
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std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
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Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
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MachinePointerInfo(), false, false, false, 0));
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Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
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MachinePointerInfo(), false, false, false, 0));
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}
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/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
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/// INT_TO_FP operation of the specified operand when the target requests that
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/// we expand it. At this point, we know that the result and operand types are
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@ -3041,14 +3143,33 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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RTLIB::SQRT_PPCF128));
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break;
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case ISD::FSIN:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_F128,
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RTLIB::SIN_PPCF128));
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case ISD::FCOS: {
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EVT VT = Node->getValueType(0);
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bool isSIN = Node->getOpcode() == ISD::FSIN;
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// Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
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// fcos which share the same operand and both are used.
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if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
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isSinCosLibcallAvailable(Node, TLI))
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&& useSinCos(Node)) {
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SDVTList VTs = DAG.getVTList(VT, VT);
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Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
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if (!isSIN)
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Tmp1 = Tmp1.getValue(1);
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Results.push_back(Tmp1);
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} else if (isSIN) {
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Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
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RTLIB::SIN_F80, RTLIB::SIN_F128,
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RTLIB::SIN_PPCF128));
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} else {
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Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_F128,
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RTLIB::COS_PPCF128));
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}
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break;
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case ISD::FCOS:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
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RTLIB::COS_F80, RTLIB::COS_F128,
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RTLIB::COS_PPCF128));
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}
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case ISD::FSINCOS:
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// Expand into sincos libcall.
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ExpandSinCosLibCall(Node, Results);
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break;
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case ISD::FLOG:
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Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
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@ -3181,7 +3302,6 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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case ISD::UREM:
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case ISD::SREM: {
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EVT VT = Node->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, VT);
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bool isSigned = Node->getOpcode() == ISD::SREM;
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unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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@ -3192,6 +3312,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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// If div is legal, it's better to do the normal expansion
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!TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
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useDivRem(Node, isSigned, false))) {
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SDVTList VTs = DAG.getVTList(VT, VT);
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
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} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
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// X % Y -> X-X/Y*Y
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@ -140,6 +140,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::FSQRT: return "fsqrt";
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case ISD::FSIN: return "fsin";
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case ISD::FCOS: return "fcos";
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case ISD::FSINCOS: return "fsincos";
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case ISD::FTRUNC: return "ftrunc";
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case ISD::FFLOOR: return "ffloor";
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case ISD::FCEIL: return "fceil";
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@ -340,6 +340,13 @@ static void InitLibcallNames(const char **Names) {
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Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
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Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
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Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
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// These are generally not available.
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Names[RTLIB::SINCOS_F32] = 0;
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Names[RTLIB::SINCOS_F64] = 0;
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Names[RTLIB::SINCOS_F80] = 0;
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Names[RTLIB::SINCOS_F128] = 0;
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Names[RTLIB::SINCOS_PPCF128] = 0;
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}
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/// InitLibcallCallingConvs - Set default libcall CallingConvs.
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@ -781,6 +781,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
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@ -1364,6 +1364,8 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
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@ -81,6 +81,7 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::FPOWI, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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setOperationAction(ISD::FLOG, MVT::f32, Expand);
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@ -421,6 +421,8 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::FSIN, MVT::f64, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FPOWI, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f64, Expand);
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@ -132,11 +132,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// We don't support sin/cos/sqrt/fmod/pow
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::FMA , MVT::f64, Legal);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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setOperationAction(ISD::FMA , MVT::f32, Legal);
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@ -759,10 +759,12 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FMA , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::FMA , MVT::f32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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@ -605,10 +605,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
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// We don't support sin/cos/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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// Expand FP immediates into loads from the stack, except for the special
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// cases we handle.
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@ -633,8 +635,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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// We don't support sin/cos/fmod
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
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// Special cases we handle for FP constants.
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addLegalFPImmediate(APFloat(+0.0f)); // xorps
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@ -644,8 +647,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
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if (!TM.Options.UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f64 , Expand);
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
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}
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} else if (!TM.Options.UseSoftFloat) {
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// f32 and f64 in x87.
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@ -659,10 +663,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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if (!TM.Options.UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f32 , Expand);
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setOperationAction(ISD::FSIN , MVT::f64 , Expand);
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setOperationAction(ISD::FCOS , MVT::f32 , Expand);
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
||||
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
|
||||
}
|
||||
addLegalFPImmediate(APFloat(+0.0)); // FLD0
|
||||
addLegalFPImmediate(APFloat(+1.0)); // FLD1
|
||||
@ -699,8 +705,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
}
|
||||
|
||||
if (!TM.Options.UnsafeFPMath) {
|
||||
setOperationAction(ISD::FSIN , MVT::f80 , Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f80 , Expand);
|
||||
setOperationAction(ISD::FSIN , MVT::f80, Expand);
|
||||
setOperationAction(ISD::FCOS , MVT::f80, Expand);
|
||||
setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
|
||||
}
|
||||
|
||||
setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
|
||||
@ -748,7 +755,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
|
||||
setOperationAction(ISD::FABS, VT, Expand);
|
||||
setOperationAction(ISD::FSIN, VT, Expand);
|
||||
setOperationAction(ISD::FSINCOS, VT, Expand);
|
||||
setOperationAction(ISD::FCOS, VT, Expand);
|
||||
setOperationAction(ISD::FSINCOS, VT, Expand);
|
||||
setOperationAction(ISD::FREM, VT, Expand);
|
||||
setOperationAction(ISD::FMA, VT, Expand);
|
||||
setOperationAction(ISD::FPOWI, VT, Expand);
|
||||
@ -1281,6 +1290,19 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
setLibcallName(RTLIB::SRA_I128, 0);
|
||||
}
|
||||
|
||||
// Combine sin / cos into one node or libcall if possible.
|
||||
if (Subtarget->hasSinCos()) {
|
||||
setLibcallName(RTLIB::SINCOS_F32, "sincosf");
|
||||
setLibcallName(RTLIB::SINCOS_F64, "sincos");
|
||||
if (Subtarget->isTargetDarwin() && Subtarget->is64Bit()) {
|
||||
// For MacOSX, we don't want to the normal expansion of a libcall to
|
||||
// sincos. We want to issue a libcall to __sincos_stret to avoid memory
|
||||
// traffic.
|
||||
setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
|
||||
setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
|
||||
}
|
||||
}
|
||||
|
||||
// We have target-specific dag combine patterns for the following nodes:
|
||||
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
|
||||
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
|
||||
@ -12014,6 +12036,50 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
|
||||
Op.getOperand(1), Op.getOperand(2));
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
|
||||
assert(Subtarget->isTargetDarwin());
|
||||
|
||||
// For MacOSX, we want to call an alternative entry point: __sincos_stret,
|
||||
// which returns the values in two XMM registers.
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
SDValue Arg = Op.getOperand(0);
|
||||
EVT ArgVT = Arg.getValueType();
|
||||
Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
|
||||
|
||||
ArgListTy Args;
|
||||
ArgListEntry Entry;
|
||||
|
||||
Entry.Node = Arg;
|
||||
Entry.Ty = ArgTy;
|
||||
Entry.isSExt = false;
|
||||
Entry.isZExt = false;
|
||||
Args.push_back(Entry);
|
||||
|
||||
const char *LibcallName = (ArgVT == MVT::f64)
|
||||
? "__sincos_stret" : "__sincosf_stret";
|
||||
SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
|
||||
|
||||
StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
|
||||
TargetLowering::
|
||||
CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
|
||||
false, false, false, false, 0,
|
||||
CallingConv::C, /*isTaillCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed*/true,
|
||||
Callee, Args, DAG, dl);
|
||||
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
|
||||
#if 1
|
||||
return CallResult.first;
|
||||
#else
|
||||
SDValue RetSin = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ArgVT,
|
||||
CallResult.first, DAG.getIntPtrConstant(0));
|
||||
SDValue RetCos = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ArgVT,
|
||||
CallResult.first, DAG.getIntPtrConstant(1));
|
||||
|
||||
SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
|
||||
return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, RetSin, RetCos);
|
||||
#endif
|
||||
}
|
||||
|
||||
/// LowerOperation - Provide custom lowering hooks for some operations.
|
||||
///
|
||||
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
@ -12096,6 +12162,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
||||
case ISD::ADD: return LowerADD(Op, DAG);
|
||||
case ISD::SUB: return LowerSUB(Op, DAG);
|
||||
case ISD::SDIV: return LowerSDIV(Op, DAG);
|
||||
case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -838,8 +838,8 @@ namespace llvm {
|
||||
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
// Utility functions to help LowerVECTOR_SHUFFLE & LowerBUILD_VECTOR
|
||||
SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
@ -155,6 +155,11 @@ const char *X86Subtarget::getBZeroEntry() const {
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool X86Subtarget::hasSinCos() const {
|
||||
return getTargetTriple().isMacOSX() &&
|
||||
!getTargetTriple().isMacOSXVersionLT(10, 9);
|
||||
}
|
||||
|
||||
/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
|
||||
/// to immediate address.
|
||||
bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
|
||||
|
||||
@ -328,6 +328,10 @@ public:
|
||||
/// memset with zero passed as the second argument. Otherwise it
|
||||
/// returns null.
|
||||
const char *getBZeroEntry() const;
|
||||
|
||||
/// This function returns true if the target has sincos() routine in its
|
||||
/// compiler runtime or math libraries.
|
||||
bool hasSinCos() const;
|
||||
|
||||
/// enablePostRAScheduler - run for Atom optimization.
|
||||
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user