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Fix a naughty header include that breaks "installed" builds.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-04-24 20:36:19 +00:00
parent 80c1ea6f9b
commit 86b7e2acc9
2 changed files with 16 additions and 6 deletions
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8
include/llvm/CodeGen/MachineScheduler.h
View File

@ -27,7 +27,6 @@
#ifndef MACHINESCHEDULER_H
#define MACHINESCHEDULER_H
#include "RegisterClassInfo.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
namespace llvm {
@ -36,6 +35,7 @@ class AliasAnalysis;
class LiveIntervals;
class MachineDominatorTree;
class MachineLoopInfo;
class RegClassInfo;
class ScheduleDAGInstrs;
/// MachineSchedContext provides enough context from the MachineScheduler pass
@ -48,10 +48,10 @@ struct MachineSchedContext {
AliasAnalysis *AA;
LiveIntervals *LIS;
RegisterClassInfo RegClassInfo;
RegisterClassInfo *RegClassInfo;
MachineSchedContext():
MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
MachineSchedContext();
virtual ~MachineSchedContext();
};
/// MachineSchedRegistry provides a selection of available machine instruction

14
lib/CodeGen/MachineScheduler.cpp
View File

@ -14,6 +14,7 @@
#define DEBUG_TYPE "misched"
#include "RegisterClassInfo.h"
#include "RegisterPressure.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineScheduler.h"
@ -51,6 +52,15 @@ static bool ViewMISchedDAGs = false;
// Machine Instruction Scheduling Pass and Registry
//===----------------------------------------------------------------------===//
MachineSchedContext::MachineSchedContext():
MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
RegClassInfo = new RegisterClassInfo();
}
MachineSchedContext::~MachineSchedContext() {
delete RegClassInfo;
}
namespace {
/// MachineScheduler runs after coalescing and before register allocation.
class MachineScheduler : public MachineSchedContext,
@ -173,7 +183,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
LIS = &getAnalysis<LiveIntervals>();
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
RegClassInfo.runOnMachineFunction(*MF);
RegClassInfo->runOnMachineFunction(*MF);
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
@ -328,7 +338,7 @@ class ScheduleDAGMI : public ScheduleDAGInstrs {
public:
ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
AA(C->AA), RegClassInfo(&C->RegClassInfo), SchedImpl(S),
AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
RPTracker(RegPressure), CurrentTop(), CurrentBottom(),
NumInstrsScheduled(0) {}