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[x86] Revert r214007: Fix PR20355 ...

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The clever way to implement signed multiplication with unsigned *is
already implemented* and tested and working correctly. The bug is
somewhere else. Re-investigating.

This will teach me to not scroll far enough to read the code that did
what I thought needed to be done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214009 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-07-26 02:14:54 +00:00
parent 47a12d8d2c
commit 86de7ad211
3 changed files with 18 additions and 14 deletions
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8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -970,6 +970,7 @@ void X86TargetLowering::resetOperationActions() {
setOperationAction(ISD::MUL, MVT::v4i32, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
setOperationAction(ISD::SUB, MVT::v16i8, Legal);
@ -1112,8 +1113,6 @@ void X86TargetLowering::resetOperationActions() {
// FIXME: Do we need to handle scalar-to-vector here?
setOperationAction(ISD::MUL, MVT::v4i32, Legal);
setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
@ -15433,9 +15432,8 @@ static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
// ints.
MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
assert((!IsSigned || Subtarget->hasSSE41()) &&
"We need PMULDQ for signed multiplies!");
unsigned Opcode = IsSigned ? X86ISD::PMULDQ : X86ISD::PMULUDQ;
unsigned Opcode =
(!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
// PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
// => <2 x i64> <ae|cg>
SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,

8
test/CodeGen/X86/pmul.ll
View File

@ -84,10 +84,10 @@ entry:
}
define <2 x i64> @f(<2 x i64> %i, <2 x i64> %j) nounwind {
; ALL-LABEL: f:
; ALL: pmuludq
; ALL: pmuludq
; ALL: pmuludq
; CHECK-LABEL: f:
; CHECK: pmuludq
; CHECK: pmuludq
; CHECK: pmuludq
entry:
; Use a call to force spills.
call void @foo()

16
test/CodeGen/X86/vector-idiv.ll
View File

@ -131,12 +131,18 @@ define <4 x i32> @test8(<4 x i32> %a) {
; SSE41: psrad $2
; SSE41: padd
; FIXME: scalarized -- there is no signed multiply in SSE.
; SSE-LABEL: test8:
; SSE: imulq
; SSE: imulq
; SSE: imulq
; SSE: imulq
; SSE: pmuludq
; SSE: pshufd $49
; SSE: pshufd $49
; SSE: pmuludq
; SSE: shufps $-35
; SSE: pshufd $-40
; SSE: psubd
; SSE: padd
; SSE: psrld $31
; SSE: psrad $2
; SSE: padd
; AVX-LABEL: test8:
; AVX: vpmuldq