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It's ok to spill a tGPR register as long as it's still allocated a low register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-08-13 05:40:51 +00:00
parent b2d3169d96
commit 86e5f7b6f8
2 changed files with 54 additions and 6 deletions
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20
lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -91,12 +91,14 @@ canFoldMemoryOperand(const MachineInstr *MI,
case ARM::tMOVgpr2gpr: {
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
!isARMLowRegister(SrcReg))
// tSpill cannot take a high register operand.
return false;
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
!isARMLowRegister(DstReg))
// tRestore cannot target a high register operand.
return false;
}
@ -114,7 +116,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
assert((RC == ARM::tGPRRegisterClass ||
(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
isARMLowRegister(SrcReg))) && "Unknown regclass!");
if (RC == ARM::tGPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
@ -130,7 +134,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
assert((RC == ARM::tGPRRegisterClass ||
(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
isARMLowRegister(DestReg))) && "Unknown regclass!");
if (RC == ARM::tGPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
@ -212,7 +218,8 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
!isARMLowRegister(SrcReg))
// tSpill cannot take a high register operand.
break;
NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
@ -220,7 +227,8 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
.addFrameIndex(FI).addImm(0));
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
!isARMLowRegister(DstReg))
// tRestore cannot target a high register operand.
break;
bool isDead = MI->getOperand(0).isDead();

40
test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin
%struct.vorbis_comment = type { i8**, i32*, i32, i8* }
@.str16 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1]
declare arm_apcscc i8* @__strcpy_chk(i8*, i8*, i32) nounwind
declare arm_apcscc i8* @__strcat_chk(i8*, i8*, i32) nounwind
define arm_apcscc i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind {
entry:
%0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=2]
%1 = call arm_apcscc i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; <i8*> [#uses=0]
%2 = call arm_apcscc i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0]
%3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; <i8***> [#uses=1]
br label %bb11
bb6: ; preds = %bb11
%4 = load i8*** %3, align 4 ; <i8**> [#uses=1]
%scevgep = getelementptr i8** %4, i32 %8 ; <i8**> [#uses=1]
%5 = load i8** %scevgep, align 4 ; <i8*> [#uses=1]
br label %bb3.i
bb3.i: ; preds = %bb3.i, %bb6
%scevgep7.i = getelementptr i8* %5, i32 0 ; <i8*> [#uses=1]
%6 = load i8* %scevgep7.i, align 1 ; <i8> [#uses=0]
br i1 undef, label %bb3.i, label %bb10
bb10: ; preds = %bb3.i
%7 = add i32 %8, 1 ; <i32> [#uses=1]
br label %bb11
bb11: ; preds = %bb10, %entry
%8 = phi i32 [ %7, %bb10 ], [ 0, %entry ] ; <i32> [#uses=3]
%9 = icmp sgt i32 undef, %8 ; <i1> [#uses=1]
br i1 %9, label %bb6, label %bb13
bb13: ; preds = %bb11
ret i8* null
}