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elimiante use of getNode that takes vector of operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29612 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-08-11 17:22:35 +00:00
parent e0e42d457e
commit 8742867f95
1 changed files with 4 additions and 3 deletions
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7
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -157,7 +157,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
unsigned CallOpc = ARMISD::CALL;
if (InFlag.Val)
Ops.push_back(InFlag);
Chain = DAG.getNode(CallOpc, NodeTys, Ops);
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
std::vector<SDOperand> ResultVals;
@@ -182,7 +182,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
return Chain;
ResultVals.push_back(Chain);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
ResultVals.size());
return Res.getValue(Op.ResNo);
}
@@ -279,7 +280,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
}
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {