mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add DEBUG_VALUE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -477,6 +477,14 @@ def COPY_TO_REGCLASS : Instruction {
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let neverHasSideEffects = 1;
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let neverHasSideEffects = 1;
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let isAsCheapAsAMove = 1;
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let isAsCheapAsAMove = 1;
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}
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}
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def DEBUG_VALUE : Instruction {
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let OutOperandList = (ops);
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let InOperandList = (ops unknown:$value, i64imm:$offset, unknown:$meta);
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let AsmString = "DEBUG_VALUE";
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let Namespace = "TargetInstrInfo";
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let neverHasSideEffects = 1;
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let isAsCheapAsAMove = 1;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@@ -88,7 +88,10 @@ public:
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/// only needed in cases where the register classes implied by the
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. The actual MachineInstrs to perform
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/// instructions are insufficient. The actual MachineInstrs to perform
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/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
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/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
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COPY_TO_REGCLASS = 10
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COPY_TO_REGCLASS = 10,
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// DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DEBUG_VALUE = 11
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};
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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unsigned getNumOpcodes() const { return NumOpcodes; }
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@@ -34,7 +34,8 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "COPY_TO_REGCLASS") continue;
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R->getName() == "COPY_TO_REGCLASS" ||
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R->getName() == "DEBUG_VALUE") continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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@@ -111,7 +112,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "INSERT_SUBREG" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "IMPLICIT_DEF" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "SUBREG_TO_REG" ||
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R->getName() == "COPY_TO_REGCLASS") {
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R->getName() == "COPY_TO_REGCLASS" ||
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R->getName() == "DEBUG_VALUE") {
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o << " 0U,\n";
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o << " 0U,\n";
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continue;
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continue;
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}
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}
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@@ -149,7 +151,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
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InstName == "INSERT_SUBREG" ||
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InstName == "INSERT_SUBREG" ||
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InstName == "IMPLICIT_DEF" ||
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InstName == "IMPLICIT_DEF" ||
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InstName == "SUBREG_TO_REG" ||
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InstName == "SUBREG_TO_REG" ||
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InstName == "COPY_TO_REGCLASS") continue;
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InstName == "COPY_TO_REGCLASS" ||
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InstName == "DEBUG_VALUE") continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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const std::vector<RecordVal> &Vals = R->getValues();
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const std::vector<RecordVal> &Vals = R->getValues();
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@@ -337,6 +337,11 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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throw "Could not find 'COPY_TO_REGCLASS' instruction!";
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throw "Could not find 'COPY_TO_REGCLASS' instruction!";
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const CodeGenInstruction *COPY_TO_REGCLASS = &I->second;
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const CodeGenInstruction *COPY_TO_REGCLASS = &I->second;
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I = getInstructions().find("DEBUG_VALUE");
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if (I == Instructions.end())
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throw "Could not find 'DEBUG_VALUE' instruction!";
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const CodeGenInstruction *DEBUG_VALUE = &I->second;
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// Print out the rest of the instructions now.
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// Print out the rest of the instructions now.
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(INLINEASM);
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NumberedInstructions.push_back(INLINEASM);
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@@ -349,6 +354,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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NumberedInstructions.push_back(IMPLICIT_DEF);
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NumberedInstructions.push_back(IMPLICIT_DEF);
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NumberedInstructions.push_back(SUBREG_TO_REG);
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NumberedInstructions.push_back(SUBREG_TO_REG);
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NumberedInstructions.push_back(COPY_TO_REGCLASS);
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NumberedInstructions.push_back(COPY_TO_REGCLASS);
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NumberedInstructions.push_back(DEBUG_VALUE);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI &&
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if (&II->second != PHI &&
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&II->second != INLINEASM &&
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&II->second != INLINEASM &&
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@@ -360,7 +366,8 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&II->second != INSERT_SUBREG &&
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&II->second != INSERT_SUBREG &&
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&II->second != IMPLICIT_DEF &&
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&II->second != IMPLICIT_DEF &&
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&II->second != SUBREG_TO_REG &&
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&II->second != SUBREG_TO_REG &&
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&II->second != COPY_TO_REGCLASS)
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&II->second != COPY_TO_REGCLASS &&
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&II->second != DEBUG_VALUE)
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NumberedInstructions.push_back(&II->second);
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NumberedInstructions.push_back(&II->second);
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}
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}
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@@ -345,7 +345,8 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
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R->getName() != "INSERT_SUBREG" &&
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R->getName() != "INSERT_SUBREG" &&
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R->getName() != "IMPLICIT_DEF" &&
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R->getName() != "IMPLICIT_DEF" &&
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R->getName() != "SUBREG_TO_REG" &&
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R->getName() != "SUBREG_TO_REG" &&
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R->getName() != "COPY_TO_REGCLASS")
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R->getName() != "COPY_TO_REGCLASS" &&
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R->getName() != "DEBUG_VALUE")
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throw R->getName() + " doesn't have a field named '" +
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throw R->getName() + " doesn't have a field named '" +
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Val->getValue() + "'!";
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Val->getValue() + "'!";
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return;
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return;
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