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R600/SI: Fix 64-bit private loads.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204630 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-03-24 17:50:46 +00:00
parent 657c472bb0
commit 875870fdb4
2 changed files with 69 additions and 9 deletions
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18
lib/Target/R600/SIISelLowering.cpp
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@@ -739,12 +739,28 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
}
EVT MemVT = Load->getMemoryVT();
assert(!MemVT.isVector() && "Private loads should be scalarized");
assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
DAG.getConstant(2, MVT::i32));
Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
Load->getChain(), Ptr,
DAG.getTargetConstant(0, MVT::i32),
Op.getOperand(2));
if (MemVT.getSizeInBits() == 64) {
SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
DAG.getConstant(1, MVT::i32));
SDValue LoadUpper = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
Load->getChain(), IncPtr,
DAG.getTargetConstant(0, MVT::i32),
Op.getOperand(2));
Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ret, LoadUpper);
}
MergedValues[0] = Ret;
return DAG.getMergeValues(MergedValues, 2, DL);