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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98769 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-03-17 21:16:45 +00:00
parent 89ef7b797a
commit 87949d4d5a
1 changed files with 12 additions and 16 deletions
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28
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -55,12 +55,12 @@ namespace {
const std::vector<MachineConstantPoolEntry> *MCPEs; const std::vector<MachineConstantPoolEntry> *MCPEs;
const std::vector<MachineJumpTableEntry> *MJTEs; const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC; bool IsPIC;
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineModuleInfo>(); AU.addRequired<MachineModuleInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
static char ID; static char ID;
public: public:
ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
@ -68,7 +68,7 @@ namespace {
TD(tm.getTargetData()), TM(tm), TD(tm.getTargetData()), TM(tm),
MCE(mce), MCPEs(0), MJTEs(0), MCE(mce), MCPEs(0), MJTEs(0),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
/// getBinaryCodeForInstr - This function, generated by the /// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for /// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions. /// machine instructions.
@ -163,7 +163,7 @@ namespace {
char ARMCodeEmitter::ID = 0; char ARMCodeEmitter::ID = 0;
/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
/// code to the specified MCE object. /// code to the specified MCE object.
FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
JITCodeEmitter &JCE) { JITCodeEmitter &JCE) {
@ -617,8 +617,7 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
} }
} }
unsigned ARMCodeEmitter::getMachineSoRegOpValue( unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
const MachineInstr &MI,
const TargetInstrDesc &TID, const TargetInstrDesc &TID,
const MachineOperand &MO, const MachineOperand &MO,
unsigned OpIdx) { unsigned OpIdx) {
@ -690,7 +689,7 @@ unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
} }
unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
const TargetInstrDesc &TID) const { const TargetInstrDesc &TID) const {
for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
const MachineOperand &MO = MI.getOperand(i-1); const MachineOperand &MO = MI.getOperand(i-1);
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
@ -699,8 +698,7 @@ unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
return 0; return 0;
} }
void ARMCodeEmitter::emitDataProcessingInstruction( void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
const MachineInstr &MI,
unsigned ImplicitRd, unsigned ImplicitRd,
unsigned ImplicitRn) { unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
@ -765,8 +763,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(
emitWordLE(Binary); emitWordLE(Binary);
} }
void ARMCodeEmitter::emitLoadStoreInstruction( void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
const MachineInstr &MI,
unsigned ImplicitRd, unsigned ImplicitRd,
unsigned ImplicitRn) { unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
@ -841,7 +838,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(
} }
void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRn) { unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask; unsigned Form = TID.TSFlags & ARMII::FormMask;
bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
@ -1238,8 +1235,7 @@ void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
emitWordLE(Binary); emitWordLE(Binary);
} }
void ARMCodeEmitter::emitVFPConversionInstruction( void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
unsigned Form = TID.TSFlags & ARMII::FormMask; unsigned Form = TID.TSFlags & ARMII::FormMask;
@ -1329,8 +1325,8 @@ void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
emitWordLE(Binary); emitWordLE(Binary);
} }
void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction( void
const MachineInstr &MI) { ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;