From 879b071bf539163f90a5ef449d3e6a9ec73faa2f Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 23 May 2013 15:43:05 +0000 Subject: [PATCH] R600: Hide symbols of implementation details. Also removes an unused function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUInstrInfo.cpp | 21 ------- lib/Target/R600/AMDILCFGStructurizer.cpp | 61 ++++++------------- .../R600/MCTargetDesc/AMDGPUAsmBackend.cpp | 4 ++ lib/Target/R600/SIISelLowering.cpp | 2 +- 4 files changed, 25 insertions(+), 63 deletions(-) diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index 30f736c84c2..45d886da0f0 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -99,27 +99,6 @@ bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, return false; } -MachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) { - MachineBasicBlock::iterator tmp = MBB->end(); - if (!MBB->size()) { - return MBB->end(); - } - while (--tmp) { - if (tmp->getOpcode() == AMDGPU::ENDLOOP - || tmp->getOpcode() == AMDGPU::ENDIF - || tmp->getOpcode() == AMDGPU::ELSE) { - if (tmp == MBB->begin()) { - return tmp; - } else { - continue; - } - } else { - return ++tmp; - } - } - return MBB->end(); -} - void AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp index b0cd0f9756a..fcb5b7ed4b7 100644 --- a/lib/Target/R600/AMDILCFGStructurizer.cpp +++ b/lib/Target/R600/AMDILCFGStructurizer.cpp @@ -57,7 +57,7 @@ STATISTIC(numClonedInstr, "CFGStructurizer cloned instructions"); // Miscellaneous utility for CFGStructurizer. // //===----------------------------------------------------------------------===// -namespace llvmCFGStruct { +namespace { #define SHOWNEWINSTR(i) \ if (DEBUGME) errs() << "New instr: " << *i << "\n" @@ -98,7 +98,7 @@ void ReverseVector(SmallVector &Src) { } } -} //end namespace llvmCFGStruct +} // end anonymous namespace //===----------------------------------------------------------------------===// // @@ -106,7 +106,7 @@ void ReverseVector(SmallVector &Src) { // //===----------------------------------------------------------------------===// -namespace llvmCFGStruct { +namespace { template struct CFGStructTraits { }; @@ -142,7 +142,7 @@ public: LandInformation() : landBlk(NULL) {} }; -} //end of namespace llvmCFGStruct +} // end anonymous namespace //===----------------------------------------------------------------------===// // @@ -150,7 +150,7 @@ public: // //===----------------------------------------------------------------------===// -namespace llvmCFGStruct { +namespace { // bixia TODO: port it to BasicBlock, not just MachineBasicBlock. template class CFGStructurizer { @@ -2446,7 +2446,7 @@ CFGStructurizer::findNearestCommonPostDom return commonDom; } //findNearestCommonPostDom -} //end namespace llvm +} // end anonymous namespace //todo: move-end @@ -2458,9 +2458,7 @@ CFGStructurizer::findNearestCommonPostDom //===----------------------------------------------------------------------===// -using namespace llvmCFGStruct; - -namespace llvm { +namespace { class AMDGPUCFGStructurizer : public MachineFunctionPass { public: typedef MachineInstr InstructionType; @@ -2480,12 +2478,9 @@ protected: public: AMDGPUCFGStructurizer(char &pid, TargetMachine &tm); const TargetInstrInfo *getTargetInstrInfo() const; - -private: - }; -} //end of namespace llvm +} // end anonymous namespace AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm) : MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()), TRI(static_cast(tm.getRegisterInfo())) { @@ -2501,9 +2496,7 @@ const TargetInstrInfo *AMDGPUCFGStructurizer::getTargetInstrInfo() const { //===----------------------------------------------------------------------===// -using namespace llvmCFGStruct; - -namespace llvm { +namespace { class AMDGPUCFGPrepare : public AMDGPUCFGStructurizer { public: static char ID; @@ -2515,13 +2508,10 @@ public: virtual void getAnalysisUsage(AnalysisUsage &AU) const; bool runOnMachineFunction(MachineFunction &F); - -private: - }; char AMDGPUCFGPrepare::ID = 0; -} //end of namespace llvm +} // end anonymous namespace AMDGPUCFGPrepare::AMDGPUCFGPrepare(TargetMachine &tm) : AMDGPUCFGStructurizer(ID, tm ) { @@ -2545,9 +2535,7 @@ void AMDGPUCFGPrepare::getAnalysisUsage(AnalysisUsage &AU) const { //===----------------------------------------------------------------------===// -using namespace llvmCFGStruct; - -namespace llvm { +namespace { class AMDGPUCFGPerform : public AMDGPUCFGStructurizer { public: static char ID; @@ -2557,13 +2545,10 @@ public: virtual const char *getPassName() const; virtual void getAnalysisUsage(AnalysisUsage &AU) const; bool runOnMachineFunction(MachineFunction &F); - -private: - }; char AMDGPUCFGPerform::ID = 0; -} //end of namespace llvm +} // end anonymous namespace AMDGPUCFGPerform::AMDGPUCFGPerform(TargetMachine &tm) : AMDGPUCFGStructurizer(ID, tm) { @@ -2587,7 +2572,7 @@ void AMDGPUCFGPerform::getAnalysisUsage(AnalysisUsage &AU) const { // //===----------------------------------------------------------------------===// -namespace llvmCFGStruct { +namespace { // this class is tailor to the AMDGPU backend template<> struct CFGStructTraits { @@ -3024,28 +3009,22 @@ struct CFGStructTraits { return &pass.getAnalysis(); } }; // template class CFGStructTraits -} //end of namespace llvm +} // end anonymous namespace // createAMDGPUCFGPreparationPass- Returns a pass -FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm - ) { - return new AMDGPUCFGPrepare(tm ); +FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm) { + return new AMDGPUCFGPrepare(tm); } bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) { - return llvmCFGStruct::CFGStructurizer().prepare(func, - *this, - TRI); + return CFGStructurizer().prepare(func, *this, TRI); } // createAMDGPUCFGStructurizerPass- Returns a pass -FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm - ) { - return new AMDGPUCFGPerform(tm ); +FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm) { + return new AMDGPUCFGPerform(tm); } bool AMDGPUCFGPerform::runOnMachineFunction(MachineFunction &func) { - return llvmCFGStruct::CFGStructurizer().run(func, - *this, - TRI); + return CFGStructurizer().run(func, *this, TRI); } diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp index a3397f3a420..9a369039b27 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -82,6 +82,8 @@ void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, // ELFAMDGPUAsmBackend class //===----------------------------------------------------------------------===// +namespace { + class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend { public: ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { } @@ -91,6 +93,8 @@ public: } }; +} // end anonymous namespace + MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, StringRef TT, StringRef CPU) { return new ELFAMDGPUAsmBackend(T); diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index fb06889db6c..383f88171d6 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -706,7 +706,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node, } /// \brief Helper function for adjustWritemask -unsigned SubIdx2Lane(unsigned Idx) { +static unsigned SubIdx2Lane(unsigned Idx) { switch (Idx) { default: return 0; case AMDGPU::sub0: return 0;