6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-15 19:24:33 +00:00
Code Issues Projects Releases Wiki Activity

Update AArch64 ELF relocations to ABI 1.0

Browse Source 
This mostly entails adding relocations, however there are a couple of
changes to existing relocations:

1. R_AARCH64_NONE is defined to be zero rather than 256

R_AARCH64_NONE has been defined to be zero for a long time elsewhere
e.g. binutils and glibc since the submission of the AArch64 port in
2012 so this is required for compatibility.

2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21

I don't think there is any way for relocation names to leak out of LLVM
so this should not break anything.

Tested with check-all with no regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Will Newton
2014-11-26 10:49:18 +00:00
parent 10c8f38047
commit 87a2f3751c
11 changed files with 139 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64
View File

Binary file not shown.

43
test/tools/llvm-readobj/Inputs/relocs.py
View File

@@ -591,7 +591,7 @@ class Relocs_Elf_PPC64(Enum):
R_PPC64_TLSLD = 108
class Relocs_Elf_AArch64(Enum):
R_AARCH64_NONE = 0x100
R_AARCH64_NONE = 0
R_AARCH64_ABS64 = 0x101
R_AARCH64_ABS32 = 0x102
R_AARCH64_ABS16 = 0x103
@@ -611,6 +611,7 @@ class Relocs_Elf_AArch64(Enum):
R_AARCH64_LD_PREL_LO19 = 0x111
R_AARCH64_ADR_PREL_LO21 = 0x112
R_AARCH64_ADR_PREL_PG_HI21 = 0x113
R_AARCH64_ADR_PREL_PG_HI21_NC = 0x114
R_AARCH64_ADD_ABS_LO12_NC = 0x115
R_AARCH64_LDST8_ABS_LO12_NC = 0x116
R_AARCH64_TSTBR14 = 0x117
@@ -620,11 +621,39 @@ class Relocs_Elf_AArch64(Enum):
R_AARCH64_LDST16_ABS_LO12_NC = 0x11c
R_AARCH64_LDST32_ABS_LO12_NC = 0x11d
R_AARCH64_LDST64_ABS_LO12_NC = 0x11e
R_AARCH64_MOVW_PREL_G0 = 0x11f
R_AARCH64_MOVW_PREL_G0_NC = 0x120
R_AARCH64_MOVW_PREL_G1 = 0x121
R_AARCH64_MOVW_PREL_G1_NC = 0x122
R_AARCH64_MOVW_PREL_G2 = 0x123
R_AARCH64_MOVW_PREL_G2_NC = 0x124
R_AARCH64_MOVW_PREL_G3 = 0x125
R_AARCH64_LDST128_ABS_LO12_NC = 0x12b
R_AARCH64_MOVW_GOTOFF_G0 = 0x12c
R_AARCH64_MOVW_GOTOFF_G0_NC = 0x12d
R_AARCH64_MOVW_GOTOFF_G1 = 0x12e
R_AARCH64_MOVW_GOTOFF_G1_NC = 0x12f
R_AARCH64_MOVW_GOTOFF_G2 = 0x130
R_AARCH64_MOVW_GOTOFF_G2_NC = 0x131
R_AARCH64_MOVW_GOTOFF_G3 = 0x132
R_AARCH64_GOTREL64 = 0x133
R_AARCH64_GOTREL32 = 0x134
R_AARCH64_GOT_LD_PREL19 = 0x135
R_AARCH64_LD64_GOTOFF_LO15 = 0x136
R_AARCH64_ADR_GOT_PAGE = 0x137
R_AARCH64_LD64_GOT_LO12_NC = 0x138
R_AARCH64_LD64_GOTPAGE_LO15 = 0x139
R_AARCH64_TLSGD_ADR_PREL21 = 0x200
R_AARCH64_TLSGD_ADR_PAGE21 = 0x201
R_AARCH64_TLSGD_ADD_LO12_NC = 0x202
R_AARCH64_TLSGD_MOVW_G1 = 0x203
R_AARCH64_TLSGD_MOVW_G0_NC = 0x204
R_AARCH64_TLSLD_ADR_PREL21 = 0x205
R_AARCH64_TLSLD_ADR_PAGE21 = 0x206
R_AARCH64_TLSLD_ADD_LO12_NC = 0x207
R_AARCH64_TLSLD_MOVW_G1 = 0x208
R_AARCH64_TLSLD_MOVW_G0_NC = 0x209
R_AARCH64_TLSLD_LD_PREL19 = 0x20a
R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 0x20b
R_AARCH64_TLSLD_MOVW_DTPREL_G1 = 0x20c
R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 0x20d
@@ -662,10 +691,20 @@ class Relocs_Elf_AArch64(Enum):
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 0x22d
R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 0x22e
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 0x22f
R_AARCH64_TLSDESC_ADR_PAGE = 0x232
R_AARCH64_TLSDESC_LD_PREL19 = 0x230
R_AARCH64_TLSDESC_ADR_PREL21 = 0x231
R_AARCH64_TLSDESC_ADR_PAGE21 = 0x232
R_AARCH64_TLSDESC_LD64_LO12_NC = 0x233
R_AARCH64_TLSDESC_ADD_LO12_NC = 0x234
R_AARCH64_TLSDESC_OFF_G1 = 0x235
R_AARCH64_TLSDESC_OFF_G0_NC = 0x236
R_AARCH64_TLSDESC_LDR = 0x237
R_AARCH64_TLSDESC_ADD = 0x238
R_AARCH64_TLSDESC_CALL = 0x239
R_AARCH64_TLSLE_LDST128_TPREL_LO12 = 0x23a
R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC = 0x23b
R_AARCH64_TLSLD_LDST128_DTPREL_LO12 = 0x23c
R_AARCH64_TLSLD_LDST128_DTPREL_LO12_NC = 0x23d
R_AARCH64_COPY = 0x400
R_AARCH64_GLOB_DAT = 0x401
R_AARCH64_JUMP_SLOT = 0x402