6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-16 00:33:10 +00:00
Code Issues Projects Releases Wiki Activity

R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-05-09 16:42:16 +00:00
parent bfaccd494f
commit 87b983680c
5 changed files with 20 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -267,6 +267,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
}
setTargetDAGCombine(ISD::MUL);
setTargetDAGCombine(ISD::SELECT_CC);
}
//===----------------------------------------------------------------------===//
@ -748,16 +749,16 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
}
/// \brief Generate Min/Max node
SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
SelectionDAG &DAG) const {
SDLoc DL(Op);
EVT VT = Op.getValueType();
SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue True = Op.getOperand(2);
SDValue False = Op.getOperand(3);
SDValue CC = Op.getOperand(4);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue True = N->getOperand(2);
SDValue False = N->getOperand(3);
SDValue CC = N->getOperand(4);
if (VT != MVT::f32 ||
!((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
@ -804,7 +805,7 @@ SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
case ISD::SETCC_INVALID:
llvm_unreachable("Invalid setcc condcode!");
}
return Op;
return SDValue();
}
SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
@ -1283,6 +1284,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
simplifyI24(N1, DCI);
return SDValue();
}
case ISD::SELECT_CC: {
return CombineMinMax(N, DAG);
}
}
return SDValue();
}

2
lib/Target/R600/AMDGPUISelLowering.h
View File

@ -107,7 +107,7 @@ public:
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
const char* getTargetNodeName(unsigned Opcode) const override;
virtual SDNode *PostISelFolding(MachineSDNode *N,

12
lib/Target/R600/R600ISelLowering.cpp
View File

@ -986,13 +986,6 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
}
// Possible Min/Max pattern
SDValue MinMax = LowerMinMax(Op, DAG);
if (MinMax.getNode()) {
return MinMax;
}
// If we make it this for it means we have no native instructions to handle
// this SELECT_CC, so we must lower it.
SDValue HWTrue, HWFalse;
@ -1672,6 +1665,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
}
case ISD::SELECT_CC: {
// Try common optimizations
SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
if (Ret.getNode())
return Ret;
// fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
// selectcc x, y, a, b, inv(cc)
//

6
lib/Target/R600/SIISelLowering.cpp
View File

@ -902,12 +902,6 @@ SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc DL(Op);
// Possible Min/Max pattern
SDValue MinMax = LowerMinMax(Op, DAG);
if (MinMax.getNode()) {
return MinMax;
}
SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
}

2
test/CodeGen/R600/pv.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=r600 | FileCheck %s
;CHECK: DOT4 * T{{[0-9]\.W}} (MASKED)
;CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X
;CHECK: MAX T{{[0-9].[XYZW]}}, PV.X, 0.0
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 {
main_body: