From 87e3caf81939db20d2359bd38df2ed206040026d Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sun, 3 May 2009 15:50:18 +0000
Subject: [PATCH] Handle implicit zext in a better way. Shamelessly stolen from
 x86 backend. Thanks for Dan Gohman for suggestion!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70782 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/MSP430/MSP430InstrInfo.td | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index a7d9e79095a..021e8bbeefc 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -209,6 +209,22 @@ def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
                 "mov.b\t{$src, $dst}",
                 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
 
+// Any instruction that defines a 8-bit result leaves the high half of the
+// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
+// be copying from a truncate, but any other 8-bit operation will zero-extend
+// up to 16 bits.
+def def8 : PatLeaf<(i8 GR8:$src), [{
+  return N->getOpcode() != ISD::TRUNCATE &&
+         N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+         N->getOpcode() != ISD::CopyFromReg;
+}]>;
+
+// In the case of a 8-bit def that is known to implicitly zero-extend,
+// we can use a SUBREG_TO_REG.
+def : Pat<(i16 (zext def8:$src)),
+          (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>;
+
+
 def MOV8mi  : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
                 "mov.b\t{$src, $dst}",
                 [(store (i8 imm:$src), addr:$dst)]>;