6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-31 08:16:47 +00:00
Code Issues Projects Releases Wiki Activity

RegAllocBigBlock doesn't need LiveVariables either.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46488 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2008-01-29 02:32:13 +00:00
parent 6be48d49cf
commit 8822eabe36
1 changed files with 2 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
lib/CodeGen/RegAllocBigBlock.cpp
View File

@@ -97,10 +97,6 @@ namespace {
/// etc) /// etc)
const MRegisterInfo *RegInfo; const MRegisterInfo *RegInfo;
/// LV - Our generic LiveVariables pointer
///
LiveVariables *LV;
typedef SmallVector<unsigned, 2> VRegTimes; typedef SmallVector<unsigned, 2> VRegTimes;
/// VRegReadTable - maps VRegs in a BB to the set of times they are read /// VRegReadTable - maps VRegs in a BB to the set of times they are read
@@ -182,7 +178,6 @@ namespace {
/// getAnalaysisUsage - declares the required analyses /// getAnalaysisUsage - declares the required analyses
/// ///
virtual void getAnalysisUsage(AnalysisUsage &AU) const { virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<LiveVariables>();
AU.addRequiredID(PHIEliminationID); AU.addRequiredID(PHIEliminationID);
AU.addRequiredID(TwoAddressInstructionPassID); AU.addRequiredID(TwoAddressInstructionPassID);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
@@ -528,9 +523,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
Ops.push_back(OpNum); Ops.push_back(OpNum);
if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) { if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
++NumFolded; ++NumFolded;
// Since we changed the address of MI, make sure to update live variables FMI->copyKillDeadInfo(MI);
// to know that the new instruction has the properties of the old one.
LV->instructionChanged(MI, FMI);
return MBB.insert(MBB.erase(MI), FMI); return MBB.insert(MBB.erase(MI), FMI);
} }
@@ -832,11 +825,8 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Finally, if this is a noop copy instruction, zap it. // Finally, if this is a noop copy instruction, zap it.
unsigned SrcReg, DstReg; unsigned SrcReg, DstReg;
if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
LV->removeVirtualRegistersKilled(MI);
LV->removeVirtualRegistersDead(MI);
MBB.erase(MI); MBB.erase(MI);
}
} }
MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
@@ -857,7 +847,6 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
MF = &Fn; MF = &Fn;
TM = &Fn.getTarget(); TM = &Fn.getTarget();
RegInfo = TM->getRegisterInfo(); RegInfo = TM->getRegisterInfo();
LV = &getAnalysis<LiveVariables>();
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);