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RegAllocBigBlock doesn't need LiveVariables either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46488 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -97,10 +97,6 @@ namespace {
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/// etc)
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/// etc)
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const MRegisterInfo *RegInfo;
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const MRegisterInfo *RegInfo;
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/// LV - Our generic LiveVariables pointer
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///
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LiveVariables *LV;
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typedef SmallVector<unsigned, 2> VRegTimes;
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typedef SmallVector<unsigned, 2> VRegTimes;
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/// VRegReadTable - maps VRegs in a BB to the set of times they are read
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/// VRegReadTable - maps VRegs in a BB to the set of times they are read
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@@ -182,7 +178,6 @@ namespace {
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/// getAnalaysisUsage - declares the required analyses
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/// getAnalaysisUsage - declares the required analyses
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///
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///
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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@@ -528,9 +523,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
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Ops.push_back(OpNum);
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Ops.push_back(OpNum);
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if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
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if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) {
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++NumFolded;
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++NumFolded;
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// Since we changed the address of MI, make sure to update live variables
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FMI->copyKillDeadInfo(MI);
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// to know that the new instruction has the properties of the old one.
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LV->instructionChanged(MI, FMI);
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return MBB.insert(MBB.erase(MI), FMI);
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return MBB.insert(MBB.erase(MI), FMI);
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}
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}
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@@ -832,11 +825,8 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Finally, if this is a noop copy instruction, zap it.
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// Finally, if this is a noop copy instruction, zap it.
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unsigned SrcReg, DstReg;
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unsigned SrcReg, DstReg;
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if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) {
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if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
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LV->removeVirtualRegistersKilled(MI);
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LV->removeVirtualRegistersDead(MI);
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MBB.erase(MI);
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MBB.erase(MI);
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}
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}
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}
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MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
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MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
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@@ -857,7 +847,6 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) {
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MF = &Fn;
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MF = &Fn;
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TM = &Fn.getTarget();
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TM = &Fn.getTarget();
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RegInfo = TM->getRegisterInfo();
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RegInfo = TM->getRegisterInfo();
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LV = &getAnalysis<LiveVariables>();
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PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
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PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
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