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https://github.com/c64scene-ar/llvm-6502.git
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[NVPTX] Add support for native SIGN_EXTEND_INREG where available
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185330 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
9bc8feeb4f
commit
8834184a46
@ -138,10 +138,12 @@ NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
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setOperationAction(ISD::BR_CC, MVT::i16, Expand);
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setOperationAction(ISD::BR_CC, MVT::i16, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Expand);
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setOperationAction(ISD::BR_CC, MVT::i64, Expand);
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setOperationAction(ISD::BR_CC, MVT::i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Expand);
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// Some SIGN_EXTEND_INREG can be done using cvt instruction.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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// For others we will expand to a SHL/SRA pair.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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if (nvptxSubtarget.hasROT64()) {
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if (nvptxSubtarget.hasROT64()) {
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@ -298,6 +298,7 @@ multiclass F2<string OpcStr, SDNode OpNode> {
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// General Type Conversion
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// General Type Conversion
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//-----------------------------------
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//-----------------------------------
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let neverHasSideEffects = 1 in {
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// Generate a cvt to the given type from all possible types.
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// Generate a cvt to the given type from all possible types.
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// Each instance takes a CvtMode immediate that defines the conversion mode to
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// Each instance takes a CvtMode immediate that defines the conversion mode to
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// use. It can be CvtNONE to omit a conversion mode.
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// use. It can be CvtNONE to omit a conversion mode.
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@ -360,6 +361,23 @@ defm CVT_u64 : CVT_FROM_ALL<"u64", Int64Regs>;
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defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
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defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
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defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
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defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
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// This set of cvt is different from the above. The type of the source
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// and target are the same.
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//
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def CVT_INREG_s16_s8 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
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"cvt.s16.s8 \t$dst, $src;", []>;
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def CVT_INREG_s32_s8 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
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"cvt.s32.s8 \t$dst, $src;", []>;
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def CVT_INREG_s32_s16 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
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"cvt.s32.s16 \t$dst, $src;", []>;
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def CVT_INREG_s64_s8 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
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"cvt.s64.s8 \t$dst, $src;", []>;
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def CVT_INREG_s64_s16 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
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"cvt.s64.s16 \t$dst, $src;", []>;
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def CVT_INREG_s64_s32 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
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"cvt.s64.s32 \t$dst, $src;", []>;
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}
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//-----------------------------------
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//-----------------------------------
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// Integer Arithmetic
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// Integer Arithmetic
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//-----------------------------------
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//-----------------------------------
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@ -2349,6 +2367,14 @@ def : Pat<(i1 (trunc Int32Regs:$a)),
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def : Pat<(i1 (trunc Int16Regs:$a)),
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def : Pat<(i1 (trunc Int16Regs:$a)),
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(SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
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(SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
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// sext_inreg
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def : Pat<(sext_inreg Int16Regs:$a, i8), (CVT_INREG_s16_s8 Int16Regs:$a)>;
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def : Pat<(sext_inreg Int32Regs:$a, i8), (CVT_INREG_s32_s8 Int32Regs:$a)>;
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def : Pat<(sext_inreg Int32Regs:$a, i16), (CVT_INREG_s32_s16 Int32Regs:$a)>;
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def : Pat<(sext_inreg Int64Regs:$a, i8), (CVT_INREG_s64_s8 Int64Regs:$a)>;
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def : Pat<(sext_inreg Int64Regs:$a, i16), (CVT_INREG_s64_s16 Int64Regs:$a)>;
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def : Pat<(sext_inreg Int64Regs:$a, i32), (CVT_INREG_s64_s32 Int64Regs:$a)>;
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// Select instructions with 32-bit predicates
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// Select instructions with 32-bit predicates
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def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
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def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
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111
test/CodeGen/NVPTX/sext-in-reg.ll
Normal file
111
test/CodeGen/NVPTX/sext-in-reg.ll
Normal file
@ -0,0 +1,111 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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define void @one(i64 %a, i64 %b, i64* %p1, i64* %p2) {
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; CHECK: cvt.s64.s8
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; CHECK: cvt.s64.s8
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entry:
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%sext = shl i64 %a, 56
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%conv1 = ashr exact i64 %sext, 56
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%sext1 = shl i64 %b, 56
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%conv4 = ashr exact i64 %sext1, 56
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%shr = ashr i64 %a, 16
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%shr9 = ashr i64 %b, 16
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%add = add nsw i64 %conv4, %conv1
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store i64 %add, i64* %p1, align 8
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%add17 = add nsw i64 %shr9, %shr
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store i64 %add17, i64* %p2, align 8
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ret void
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}
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define void @two(i64 %a, i64 %b, i64* %p1, i64* %p2) {
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entry:
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; CHECK: cvt.s64.s32
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; CHECK: cvt.s64.s32
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%sext = shl i64 %a, 32
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%conv1 = ashr exact i64 %sext, 32
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%sext1 = shl i64 %b, 32
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%conv4 = ashr exact i64 %sext1, 32
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%shr = ashr i64 %a, 16
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%shr9 = ashr i64 %b, 16
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%add = add nsw i64 %conv4, %conv1
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store i64 %add, i64* %p1, align 8
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%add17 = add nsw i64 %shr9, %shr
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store i64 %add17, i64* %p2, align 8
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ret void
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}
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define void @three(i64 %a, i64 %b, i64* %p1, i64* %p2) {
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entry:
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; CHECK: cvt.s64.s16
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; CHECK: cvt.s64.s16
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%sext = shl i64 %a, 48
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%conv1 = ashr exact i64 %sext, 48
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%sext1 = shl i64 %b, 48
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%conv4 = ashr exact i64 %sext1, 48
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%shr = ashr i64 %a, 16
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%shr9 = ashr i64 %b, 16
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%add = add nsw i64 %conv4, %conv1
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store i64 %add, i64* %p1, align 8
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%add17 = add nsw i64 %shr9, %shr
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store i64 %add17, i64* %p2, align 8
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ret void
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}
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define void @four(i32 %a, i32 %b, i32* %p1, i32* %p2) {
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entry:
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; CHECK: cvt.s32.s8
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; CHECK: cvt.s32.s8
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%sext = shl i32 %a, 24
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%conv1 = ashr exact i32 %sext, 24
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%sext1 = shl i32 %b, 24
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%conv4 = ashr exact i32 %sext1, 24
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%shr = ashr i32 %a, 16
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%shr9 = ashr i32 %b, 16
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%add = add nsw i32 %conv4, %conv1
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store i32 %add, i32* %p1, align 4
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%add17 = add nsw i32 %shr9, %shr
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store i32 %add17, i32* %p2, align 4
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ret void
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}
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define void @five(i32 %a, i32 %b, i32* %p1, i32* %p2) {
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entry:
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; CHECK: cvt.s32.s16
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; CHECK: cvt.s32.s16
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%sext = shl i32 %a, 16
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%conv1 = ashr exact i32 %sext, 16
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%sext1 = shl i32 %b, 16
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%conv4 = ashr exact i32 %sext1, 16
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%shr = ashr i32 %a, 16
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%shr9 = ashr i32 %b, 16
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%add = add nsw i32 %conv4, %conv1
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store i32 %add, i32* %p1, align 4
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%add17 = add nsw i32 %shr9, %shr
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store i32 %add17, i32* %p2, align 4
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ret void
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}
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define void @six(i16 %a, i16 %b, i16* %p1, i16* %p2) {
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entry:
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; CHECK: cvt.s16.s8
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; CHECK: cvt.s16.s8
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%sext = shl i16 %a, 8
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%conv1 = ashr exact i16 %sext, 8
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%sext1 = shl i16 %b, 8
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%conv4 = ashr exact i16 %sext1, 8
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%shr = ashr i16 %a, 8
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%shr9 = ashr i16 %b, 8
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%add = add nsw i16 %conv4, %conv1
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store i16 %add, i16* %p1, align 4
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%add17 = add nsw i16 %shr9, %shr
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store i16 %add17, i16* %p2, align 4
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ret void
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}
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