From 8857294192bdc1992d60a14a6ff6c519ddee63e3 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 11 Sep 2013 09:59:17 +0000 Subject: [PATCH] [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics The elements of the operands should be half the width of the elements of the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsMips.td | 12 +-- lib/Target/Mips/MipsMSAInstrInfo.td | 24 ++--- test/CodeGen/Mips/msa/3r-d.ll | 138 +++++++++++++++++----------- 3 files changed, 104 insertions(+), 70 deletions(-) diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index b4872d23d75..5bec80294c8 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -814,18 +814,18 @@ def int_mips_div_u_d : GCCBuiltin<"__builtin_msa_div_u_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; def int_mips_dotp_s_h : GCCBuiltin<"__builtin_msa_dotp_s_h">, - Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_mips_dotp_s_w : GCCBuiltin<"__builtin_msa_dotp_s_w">, - Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_mips_dotp_s_d : GCCBuiltin<"__builtin_msa_dotp_s_d">, - Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_mips_dotp_u_h : GCCBuiltin<"__builtin_msa_dotp_u_h">, - Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_mips_dotp_u_w : GCCBuiltin<"__builtin_msa_dotp_u_w">, - Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_mips_dotp_u_d : GCCBuiltin<"__builtin_msa_dotp_u_d">, - Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; + Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_mips_dpadd_s_h : GCCBuiltin<"__builtin_msa_dpadd_s_h">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index a7d47908bf2..66d7f37a71d 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1238,19 +1238,19 @@ class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", int_mips_div_u_h, MSA128H>; class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", int_mips_div_u_w, MSA128W>; class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", int_mips_div_u_d, MSA128D>; -class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H>, - IsCommutable; -class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, MSA128W>, - IsCommutable; -class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, MSA128D>, - IsCommutable; +class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H, + MSA128B, MSA128B>, IsCommutable; +class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, MSA128W, + MSA128H, MSA128H>, IsCommutable; +class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, MSA128D, + MSA128W, MSA128W>, IsCommutable; -class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, MSA128H>, - IsCommutable; -class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, MSA128W>, - IsCommutable; -class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, MSA128D>, - IsCommutable; +class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, MSA128H, + MSA128B, MSA128B>, IsCommutable; +class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, MSA128W, + MSA128H, MSA128H>, IsCommutable; +class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, MSA128D, + MSA128W, MSA128W>, IsCommutable; class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, MSA128H, MSA128B, MSA128B>, diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll index 5edf8ca983e..8d4d3d4e6e9 100644 --- a/test/CodeGen/Mips/msa/3r-d.ll +++ b/test/CodeGen/Mips/msa/3r-d.ll @@ -179,134 +179,168 @@ declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_div_u_d_test ; -@llvm_mips_dotp_s_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_dotp_s_h_ARG2 = global <8 x i16> , align 16 -@llvm_mips_dotp_s_h_RES = global <8 x i16> , align 16 +@llvm_mips_dotp_s_h_ARG1 = global <16 x i8> , + align 16 +@llvm_mips_dotp_s_h_ARG2 = global <16 x i8> , + align 16 +@llvm_mips_dotp_s_h_RES = global <8 x i16> , + align 16 define void @llvm_mips_dotp_s_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_dotp_s_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<8 x i16> %0, <8 x i16> %1) + %0 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG1 + %1 = load <16 x i8>* @llvm_mips_dotp_s_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.dotp.s.h(<16 x i8> %0, <16 x i8> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_s_h_RES ret void } -declare <8 x i16> @llvm.mips.dotp.s.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.dotp.s.h(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dotp_s_h_test: -; CHECK: ld.h -; CHECK: ld.h +; CHECK: ld.b +; CHECK: ld.b ; CHECK: dotp_s.h ; CHECK: st.h ; CHECK: .size llvm_mips_dotp_s_h_test ; -@llvm_mips_dotp_s_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_dotp_s_w_ARG2 = global <4 x i32> , align 16 -@llvm_mips_dotp_s_w_RES = global <4 x i32> , align 16 +@llvm_mips_dotp_s_w_ARG1 = global <8 x i16> , + align 16 +@llvm_mips_dotp_s_w_ARG2 = global <8 x i16> , + align 16 +@llvm_mips_dotp_s_w_RES = global <4 x i32> , + align 16 define void @llvm_mips_dotp_s_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_dotp_s_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<4 x i32> %0, <4 x i32> %1) + %0 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG1 + %1 = load <8 x i16>* @llvm_mips_dotp_s_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.dotp.s.w(<8 x i16> %0, <8 x i16> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_s_w_RES ret void } -declare <4 x i32> @llvm.mips.dotp.s.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.dotp.s.w(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dotp_s_w_test: -; CHECK: ld.w -; CHECK: ld.w +; CHECK: ld.h +; CHECK: ld.h ; CHECK: dotp_s.w ; CHECK: st.w ; CHECK: .size llvm_mips_dotp_s_w_test ; -@llvm_mips_dotp_s_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_dotp_s_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_dotp_s_d_ARG1 = global <4 x i32> , + align 16 +@llvm_mips_dotp_s_d_ARG2 = global <4 x i32> , + align 16 @llvm_mips_dotp_s_d_RES = global <2 x i64> , align 16 define void @llvm_mips_dotp_s_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_dotp_s_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<2 x i64> %0, <2 x i64> %1) + %0 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG1 + %1 = load <4 x i32>* @llvm_mips_dotp_s_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.dotp.s.d(<4 x i32> %0, <4 x i32> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_s_d_RES ret void } -declare <2 x i64> @llvm.mips.dotp.s.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.dotp.s.d(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dotp_s_d_test: -; CHECK: ld.d -; CHECK: ld.d +; CHECK: ld.w +; CHECK: ld.w ; CHECK: dotp_s.d ; CHECK: st.d ; CHECK: .size llvm_mips_dotp_s_d_test ; -@llvm_mips_dotp_u_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_dotp_u_h_ARG2 = global <8 x i16> , align 16 -@llvm_mips_dotp_u_h_RES = global <8 x i16> , align 16 +@llvm_mips_dotp_u_h_ARG1 = global <16 x i8> , + align 16 +@llvm_mips_dotp_u_h_ARG2 = global <16 x i8> , + align 16 +@llvm_mips_dotp_u_h_RES = global <8 x i16> , + align 16 define void @llvm_mips_dotp_u_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_dotp_u_h_ARG2 - %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<8 x i16> %0, <8 x i16> %1) + %0 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG1 + %1 = load <16 x i8>* @llvm_mips_dotp_u_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.dotp.u.h(<16 x i8> %0, <16 x i8> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_dotp_u_h_RES ret void } -declare <8 x i16> @llvm.mips.dotp.u.h(<8 x i16>, <8 x i16>) nounwind +declare <8 x i16> @llvm.mips.dotp.u.h(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_dotp_u_h_test: -; CHECK: ld.h -; CHECK: ld.h +; CHECK: ld.b +; CHECK: ld.b ; CHECK: dotp_u.h ; CHECK: st.h ; CHECK: .size llvm_mips_dotp_u_h_test ; -@llvm_mips_dotp_u_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_dotp_u_w_ARG2 = global <4 x i32> , align 16 -@llvm_mips_dotp_u_w_RES = global <4 x i32> , align 16 +@llvm_mips_dotp_u_w_ARG1 = global <8 x i16> , + align 16 +@llvm_mips_dotp_u_w_ARG2 = global <8 x i16> , + align 16 +@llvm_mips_dotp_u_w_RES = global <4 x i32> , + align 16 define void @llvm_mips_dotp_u_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_dotp_u_w_ARG2 - %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<4 x i32> %0, <4 x i32> %1) + %0 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG1 + %1 = load <8 x i16>* @llvm_mips_dotp_u_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.dotp.u.w(<8 x i16> %0, <8 x i16> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_dotp_u_w_RES ret void } -declare <4 x i32> @llvm.mips.dotp.u.w(<4 x i32>, <4 x i32>) nounwind +declare <4 x i32> @llvm.mips.dotp.u.w(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_dotp_u_w_test: -; CHECK: ld.w -; CHECK: ld.w +; CHECK: ld.h +; CHECK: ld.h ; CHECK: dotp_u.w ; CHECK: st.w ; CHECK: .size llvm_mips_dotp_u_w_test ; -@llvm_mips_dotp_u_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_dotp_u_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_dotp_u_d_ARG1 = global <4 x i32> , + align 16 +@llvm_mips_dotp_u_d_ARG2 = global <4 x i32> , + align 16 @llvm_mips_dotp_u_d_RES = global <2 x i64> , align 16 define void @llvm_mips_dotp_u_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_dotp_u_d_ARG2 - %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<2 x i64> %0, <2 x i64> %1) + %0 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG1 + %1 = load <4 x i32>* @llvm_mips_dotp_u_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.dotp.u.d(<4 x i32> %0, <4 x i32> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_dotp_u_d_RES ret void } -declare <2 x i64> @llvm.mips.dotp.u.d(<2 x i64>, <2 x i64>) nounwind +declare <2 x i64> @llvm.mips.dotp.u.d(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_dotp_u_d_test: -; CHECK: ld.d -; CHECK: ld.d +; CHECK: ld.w +; CHECK: ld.w ; CHECK: dotp_u.d ; CHECK: st.d ; CHECK: .size llvm_mips_dotp_u_d_test