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https://github.com/c64scene-ar/llvm-6502.git
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In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
7385cafb7a
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88d724909e
@ -1991,7 +1991,7 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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if (isCalleeStructRet || isCallerStructRet)
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return false;
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// FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
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// FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
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// emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
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// the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
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// support in the assembler and linker to be used. This would need to be
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@ -19,7 +19,7 @@
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "Thumb1RegisterInfo.h"
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#include "ThumbRegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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@ -40,10 +40,9 @@ add_llvm_target(ARMCodeGen
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MLxExpansionPass.cpp
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Thumb1FrameLowering.cpp
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Thumb1InstrInfo.cpp
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Thumb1RegisterInfo.cpp
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ThumbRegisterInfo.cpp
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Thumb2ITBlockPass.cpp
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Thumb2InstrInfo.cpp
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Thumb2RegisterInfo.cpp
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Thumb2SizeReduction.cpp
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)
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@ -232,7 +232,7 @@ Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
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//===---------------------------------------------------------------------===//
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Thumb1 immediate field sometimes keep pre-scaled values. See
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Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
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ThumbRegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
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Thumb2.
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//===---------------------------------------------------------------------===//
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@ -41,7 +41,7 @@ static void
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emitSPUpdate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo &TII, DebugLoc dl,
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const Thumb1RegisterInfo &MRI,
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const ThumbRegisterInfo &MRI,
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int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
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emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
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MRI, MIFlags);
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@ -53,8 +53,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
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const ThumbRegisterInfo *RegInfo =
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static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
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if (!hasReservedCallFrame(MF)) {
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// If we have alloca, convert as follows:
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// ADJCALLSTACKDOWN -> sub, sp, sp, amount
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@ -89,8 +89,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
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const ThumbRegisterInfo *RegInfo =
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static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
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@ -327,8 +327,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
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DebugLoc dl = MBBI->getDebugLoc();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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const Thumb1RegisterInfo *RegInfo =
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static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
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const ThumbRegisterInfo *RegInfo =
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static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
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const Thumb1InstrInfo &TII =
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*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
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@ -16,7 +16,7 @@
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#include "ARMFrameLowering.h"
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#include "Thumb1InstrInfo.h"
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#include "Thumb1RegisterInfo.h"
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#include "ThumbRegisterInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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@ -15,13 +15,13 @@
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#define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "Thumb1RegisterInfo.h"
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#include "ThumbRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class Thumb1InstrInfo : public ARMBaseInstrInfo {
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Thumb1RegisterInfo RI;
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ThumbRegisterInfo RI;
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public:
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explicit Thumb1InstrInfo(const ARMSubtarget &STI);
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@ -36,7 +36,7 @@ public:
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const Thumb1RegisterInfo &getRegisterInfo() const override { return RI; }
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const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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@ -15,14 +15,14 @@
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#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2RegisterInfo.h"
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#include "ThumbRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ScheduleHazardRecognizer;
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class Thumb2InstrInfo : public ARMBaseInstrInfo {
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Thumb2RegisterInfo RI;
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ThumbRegisterInfo RI;
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public:
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explicit Thumb2InstrInfo(const ARMSubtarget &STI);
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@ -60,7 +60,7 @@ public:
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const Thumb2RegisterInfo &getRegisterInfo() const override { return RI; }
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const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI,
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@ -1,51 +0,0 @@
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//===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb2RegisterInfo.h"
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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Thumb2RegisterInfo::Thumb2RegisterInfo() : ARMBaseRegisterInfo() {}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void
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Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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const Constant *C = ConstantInt::get(
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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.setMIFlags(MIFlags);
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}
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@ -1,38 +0,0 @@
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//===- Thumb2RegisterInfo.h - Thumb-2 Register Information Impl -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_THUMB2REGISTERINFO_H
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#define LLVM_LIB_TARGET_ARM_THUMB2REGISTERINFO_H
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#include "ARMBaseRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
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public:
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Thumb2RegisterInfo();
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void
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emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
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ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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unsigned MIFlags = MachineInstr::NoFlags) const override;
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};
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}
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#endif
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@ -1,4 +1,4 @@
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//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
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//===-- ThumbRegisterInfo.cpp - Thumb-1 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -12,7 +12,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1RegisterInfo.h"
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#include "ThumbRegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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@ -38,32 +38,33 @@ extern cl::opt<bool> ReuseFrameIndexVals;
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using namespace llvm;
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Thumb1RegisterInfo::Thumb1RegisterInfo() : ARMBaseRegisterInfo() {}
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ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}
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const TargetRegisterClass *
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Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
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ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const {
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if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
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if (ARM::tGPRRegClass.hasSubClassEq(RC))
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return &ARM::tGPRRegClass;
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return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
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}
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const TargetRegisterClass *
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Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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ThumbRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
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return ARMBaseRegisterInfo::getPointerRegClass(MF, Kind);
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return &ARM::tGPRRegClass;
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void Thumb1RegisterInfo::emitLoadConstPool(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
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unsigned PredReg, unsigned MIFlags) const {
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assert((isARMLowRegister(DestReg) ||
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isVirtualRegister(DestReg)) &&
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"Thumb1 does not have ldr to high register");
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static void emitThumb1LoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, unsigned DestReg,
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unsigned SubIdx, int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) {
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MachineFunction &MF = *MBB.getParent();
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const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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@ -78,6 +79,42 @@ void Thumb1RegisterInfo::emitLoadConstPool(
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.setMIFlags(MIFlags);
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}
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static void emitThumb2LoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, unsigned DestReg,
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unsigned SubIdx, int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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const Constant *C = ConstantInt::get(
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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.setMIFlags(MIFlags);
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void ThumbRegisterInfo::emitLoadConstPool(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
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unsigned PredReg, unsigned MIFlags) const {
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MachineFunction &MF = *MBB.getParent();
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const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
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if (STI.isThumb1Only()) {
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assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) &&
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"Thumb1 does not have ldr to high register");
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return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
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PredReg, MIFlags);
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}
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return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
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PredReg, MIFlags);
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}
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/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
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@ -312,12 +349,15 @@ static unsigned convertToNonSPOpcode(unsigned Opcode) {
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return Opcode;
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}
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bool Thumb1RegisterInfo::
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rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const {
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bool ThumbRegisterInfo::rewriteFrameIndex(MachineBasicBlock::iterator II,
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unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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const MachineFunction &MF = *MBB.getParent();
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assert(MF.getSubtarget<ARMSubtarget>().isThumb1Only() &&
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"This isn't needed for thumb2!");
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DebugLoc dl = MI.getDebugLoc();
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MachineInstrBuilder MIB(*MBB.getParent(), &MI);
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unsigned Opcode = MI.getOpcode();
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@ -381,10 +421,13 @@ rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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return Offset == 0;
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}
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void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
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if (!STI.isThumb1Only())
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return ARMBaseRegisterInfo::resolveFrameIndex(MI, BaseReg, Offset);
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const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
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int Off = Offset; // ARM doesn't need the general 64-bit offsets
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unsigned i = 0;
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@ -400,18 +443,20 @@ void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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/// saveScavengerRegister - Spill the register so it can be used by the
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/// register scavenger. Return true.
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bool
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Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &UseMI,
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const TargetRegisterClass *RC,
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unsigned Reg) const {
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bool ThumbRegisterInfo::saveScavengerRegister(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
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unsigned Reg) const {
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const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>();
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if (!STI.isThumb1Only())
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return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
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// Thumb1 can't use the emergency spill slot on the stack because
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// ldr/str immediate offsets must be positive, and if we're referencing
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// off the frame pointer (if, for example, there are alloca() calls in
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// the function, the offset will be negative. Use R12 instead since that's
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// a call clobbered register that we know won't be used in Thumb1 mode.
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const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>();
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const TargetInstrInfo &TII = *STI.getInstrInfo();
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DebugLoc DL;
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AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
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@ -450,15 +495,18 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
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return true;
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}
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void
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Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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unsigned VReg = 0;
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void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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||||
MachineInstr &MI = *II;
|
||||
MachineBasicBlock &MBB = *MI.getParent();
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
||||
if (!STI.isThumb1Only())
|
||||
return ARMBaseRegisterInfo::eliminateFrameIndex(II, SPAdj, FIOperandNum,
|
||||
RS);
|
||||
|
||||
unsigned VReg = 0;
|
||||
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
DebugLoc dl = MI.getDebugLoc();
|
@ -1,4 +1,4 @@
|
||||
//===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl -*- C++ -*-===//
|
||||
//===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -7,8 +7,9 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the Thumb-1 implementation of the TargetRegisterInfo
|
||||
// class.
|
||||
// This file contains the Thumb implementation of the TargetRegisterInfo
|
||||
// class. With the exception of emitLoadConstPool Thumb2 tracks
|
||||
// ARMBaseRegisterInfo, Thumb1 overloads the functions below.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -22,9 +23,9 @@ namespace llvm {
|
||||
class ARMSubtarget;
|
||||
class ARMBaseInstrInfo;
|
||||
|
||||
struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
||||
struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
|
||||
public:
|
||||
Thumb1RegisterInfo();
|
||||
ThumbRegisterInfo();
|
||||
|
||||
const TargetRegisterClass *
|
||||
getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
Loading…
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Reference in New Issue
Block a user