6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-02 07:32:52 +00:00
Code Issues Projects Releases Wiki Activity

Add BLXi to the instruction table for disassembly purpose.

Browse Source 
A8.6.23 BLX (immediate)

rdar://problem/9212921


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-31 17:53:50 +00:00
parent 02ae9f2f27
commit 8901e6ff3d
3 changed files with 26 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1528,6 +1528,16 @@ let isBranch = 1, isTerminator = 1 in {
}
}
// BLX (immediate) -- for disassembly only
def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
"blx\t$target", [/* pattern left blank */]>,
Requires<[IsARM, HasV5T]> {
let Inst{31-25} = 0b1111101;
bits<25> target;
let Inst{23-0} = target{24-1};
let Inst{24} = target{0};
}
// Branch and Exchange Jazelle -- for disassembly only
def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
[/* For disassembly only; pattern left blank */]> {

15
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -764,7 +764,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
|| Opcode == ARM::SMC || Opcode == ARM::SVC) &&
"Unexpected Opcode");
assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
int Imm32 = 0;
if (Opcode == ARM::SMC) {
@ -787,7 +787,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
}
// Misc. Branch Instructions.
// BLX, BX
// BLX, BLXi, BX
// BX, BX_RET
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -814,6 +814,17 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return true;
}
// BLXi takes imm32 (the PC offset).
if (Opcode == ARM::BLXi) {
assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected");
// SignExtend(imm24:H:'0', 32) where imm24 = Inst{23-0} and H = Inst{24}.
unsigned Imm26 = slice(insn, 23, 0) << 2 | slice(insn, 24, 24) << 1;
int Imm32 = SignExtend32<26>(Imm26);
MI.addOperand(MCOperand::CreateImm(Imm32));
OpIdx = 1;
return true;
}
return false;
}

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -211,3 +211,6 @@
# CHECK: stc2 p2, cr4, [r9], {157}
0x9d 0x42 0x89 0xfc
# CHECK: blx #60
0x0f 0x00 0x00 0xfa