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Print "lock \t foo" instead of "lock \n foo".

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This gets gas and llc -filetype=obj to agree on the order of prefixes.

For llvm-mc we need to fix the asm parser to know that it makes a difference
on which line the "lock" is in.

Part of pr23594.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238232 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2015-05-26 18:35:10 +00:00
parent 176d1faf6a
commit 890a876e0e
12 changed files with 20 additions and 39 deletions
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2
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
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@@ -48,7 +48,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
if (TSFlags & X86II::LOCK) if (TSFlags & X86II::LOCK)
OS << "\tlock\n"; OS << "\tlock\t";
// Output CALLpcrel32 as "callq" in 64-bit mode. // Output CALLpcrel32 as "callq" in 64-bit mode.
// In Intel annotation it's always emitted as "call". // In Intel annotation it's always emitted as "call".

3
test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
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@@ -37,8 +37,7 @@ lt_init.exit: ; preds = %if.end.i, %if.then.
%4 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1] %4 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
%5 = sub i64 %4, %2 ; <i64> [#uses=1] %5 = sub i64 %4, %2 ; <i64> [#uses=1]
%6 = atomicrmw add i64* getelementptr inbounds ([1216 x i64], [1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5 monotonic %6 = atomicrmw add i64* getelementptr inbounds ([1216 x i64], [1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5 monotonic
;CHECK: lock ;CHECK: lock {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live
;CHECK-NEXT: {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live
;CHECK-NEXT: cmpl $0, ;CHECK-NEXT: cmpl $0,
;CHECK-NEXT: jne ;CHECK-NEXT: jne
%cmp = icmp eq i32 %3, 0 ; <i1> [#uses=1] %cmp = icmp eq i32 %3, 0 ; <i1> [#uses=1]

3
test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
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@@ -14,8 +14,7 @@ entry:
; CHECK: addl $1, %ebx ; CHECK: addl $1, %ebx
; CHECK: movl %edx, %ecx ; CHECK: movl %edx, %ecx
; CHECK: adcl $0, %ecx ; CHECK: adcl $0, %ecx
; CHECK: lock ; CHECK: lock cmpxchg8b ([[REG]])
; CHECK-NEXT: cmpxchg8b ([[REG]])
; CHECK-NEXT: jne ; CHECK-NEXT: jne
%0 = atomicrmw add i64* %p, i64 1 seq_cst %0 = atomicrmw add i64* %p, i64 1 seq_cst
ret void ret void

3
test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
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@@ -16,8 +16,7 @@ define void @foo(i64* %ptr) nounwind inlinehint {
entry: entry:
br label %loop br label %loop
loop: loop:
; CHECK: lock ; CHECK: lock cmpxchg8b
; CHECK-NEXT: cmpxchg8b
%pair = cmpxchg i64* %ptr, i64 0, i64 1 monotonic monotonic %pair = cmpxchg i64* %ptr, i64 0, i64 1 monotonic monotonic
%r = extractvalue { i64, i1 } %pair, 0 %r = extractvalue { i64, i1 } %pair, 0
%stored1 = icmp eq i64 %r, 0 %stored1 = icmp eq i64 %r, 0

3
test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll
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@@ -13,8 +13,7 @@ entry:
; Make sure the fence comes before the comparison, since it ; Make sure the fence comes before the comparison, since it
; clobbers EFLAGS. ; clobbers EFLAGS.
; CHECK: lock ; CHECK: lock orl {{.*}}, (%esp)
; CHECK-NEXT: orl {{.*}}, (%esp)
; CHECK-NEXT: testl [[REG:%e[a-z]+]], [[REG]] ; CHECK-NEXT: testl [[REG:%e[a-z]+]], [[REG]]
if.then: ; preds = %entry if.then: ; preds = %entry

6
test/CodeGen/X86/atomic-load-store-wide.ll
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@@ -5,8 +5,7 @@
define void @test1(i64* %ptr, i64 %val1) { define void @test1(i64* %ptr, i64 %val1) {
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
; CHECK: lock ; CHECK: lock cmpxchg8b
; CHECK-NEXT: cmpxchg8b
; CHECK-NEXT: jne ; CHECK-NEXT: jne
store atomic i64 %val1, i64* %ptr seq_cst, align 8 store atomic i64 %val1, i64* %ptr seq_cst, align 8
ret void ret void
@@ -14,8 +13,7 @@ define void @test1(i64* %ptr, i64 %val1) {
define i64 @test2(i64* %ptr) { define i64 @test2(i64* %ptr) {
; CHECK-LABEL: test2 ; CHECK-LABEL: test2
; CHECK: lock ; CHECK: lock cmpxchg8b
; CHECK-NEXT: cmpxchg8b
%val = load atomic i64, i64* %ptr seq_cst, align 8 %val = load atomic i64, i64* %ptr seq_cst, align 8
ret i64 %val ret i64 %val
} }

12
test/CodeGen/X86/atomic-minmax-i6432.ll
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@@ -11,8 +11,7 @@ define void @atomic_maxmin_i6432() {
; LINUX: seta ; LINUX: seta
; LINUX: cmovne ; LINUX: cmovne
; LINUX: cmovne ; LINUX: cmovne
; LINUX: lock ; LINUX: lock cmpxchg8b
; LINUX-NEXT: cmpxchg8b
; LINUX: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%2 = atomicrmw min i64* @sc64, i64 6 acquire %2 = atomicrmw min i64* @sc64, i64 6 acquire
; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -20,8 +19,7 @@ define void @atomic_maxmin_i6432() {
; LINUX: setb ; LINUX: setb
; LINUX: cmovne ; LINUX: cmovne
; LINUX: cmovne ; LINUX: cmovne
; LINUX: lock ; LINUX: lock cmpxchg8b
; LINUX-NEXT: cmpxchg8b
; LINUX: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%3 = atomicrmw umax i64* @sc64, i64 7 acquire %3 = atomicrmw umax i64* @sc64, i64 7 acquire
; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -29,8 +27,7 @@ define void @atomic_maxmin_i6432() {
; LINUX: seta ; LINUX: seta
; LINUX: cmovne ; LINUX: cmovne
; LINUX: cmovne ; LINUX: cmovne
; LINUX: lock ; LINUX: lock cmpxchg8b
; LINUX-NEXT: cmpxchg8b
; LINUX: jne [[LABEL]] ; LINUX: jne [[LABEL]]
%4 = atomicrmw umin i64* @sc64, i64 8 acquire %4 = atomicrmw umin i64* @sc64, i64 8 acquire
; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
@@ -38,8 +35,7 @@ define void @atomic_maxmin_i6432() {
; LINUX: setb ; LINUX: setb
; LINUX: cmovne ; LINUX: cmovne
; LINUX: cmovne ; LINUX: cmovne
; LINUX: lock ; LINUX: lock cmpxchg8b
; LINUX-NEXT: cmpxchg8b
; LINUX: jne [[LABEL]] ; LINUX: jne [[LABEL]]
ret void ret void
} }

6
test/CodeGen/X86/atomic-or.ll
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@@ -9,8 +9,7 @@ entry:
%tmp = load i64*, i64** %p.addr, align 8 %tmp = load i64*, i64** %p.addr, align 8
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: movl $2147483648, %eax ; CHECK: movl $2147483648, %eax
; CHECK: lock ; CHECK: lock orq %r{{.*}}, (%r{{.*}})
; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
%0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst %0 = atomicrmw or i64* %tmp, i64 2147483648 seq_cst
ret void ret void
} }
@@ -21,8 +20,7 @@ entry:
store i64* %p, i64** %p.addr, align 8 store i64* %p, i64** %p.addr, align 8
%tmp = load i64*, i64** %p.addr, align 8 %tmp = load i64*, i64** %p.addr, align 8
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
; CHECK: lock ; CHECK: lock orq $2147483644, (%r{{.*}})
; CHECK-NEXT: orq $2147483644, (%r{{.*}})
%0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
ret void ret void
} }

3
test/CodeGen/X86/cmpxchg16b.ll
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@@ -4,8 +4,7 @@
define void @t1(i128* nocapture %p) nounwind ssp { define void @t1(i128* nocapture %p) nounwind ssp {
entry: entry:
; CHECK: movl $1, %ebx ; CHECK: movl $1, %ebx
; CHECK: lock ; CHECK: lock cmpxchg16b
; CHECK-NEXT: cmpxchg16b
%r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
ret void ret void
} }

3
test/CodeGen/X86/i486-fence-loop.ll
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@@ -7,8 +7,7 @@
define void @gst_atomic_queue_push(i32* %addr) { define void @gst_atomic_queue_push(i32* %addr) {
; CHECK-LABEL: gst_atomic_queue_push: ; CHECK-LABEL: gst_atomic_queue_push:
; CHECK: movl (%eax), [[LHS:%e[a-z]+]] ; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
; CHECK: lock ; CHECK: lock orl
; CHECK-NEXT: orl
; CHECK: movl (%eax), [[RHS:%e[a-z]+]] ; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
; CHECK: cmpl [[LHS]], [[RHS]] ; CHECK: cmpl [[LHS]], [[RHS]]

3
test/CodeGen/X86/pr21099.ll
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@@ -2,8 +2,7 @@
define void @pr21099(i64* %p) { define void @pr21099(i64* %p) {
; CHECK-LABEL: pr21099 ; CHECK-LABEL: pr21099
; CHECK: lock ; CHECK: lock addq $-2147483648
; CHECK-NEXT: addq $-2147483648
; This number is INT32_MIN: 0x80000000UL ; This number is INT32_MIN: 0x80000000UL
%1 = atomicrmw add i64* %p, i64 -2147483648 seq_cst %1 = atomicrmw add i64* %p, i64 -2147483648 seq_cst
ret void ret void

12
test/CodeGen/X86/pr5145.ll
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@@ -7,29 +7,25 @@ define void @atomic_maxmin_i8() {
; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]:
; CHECK: movsbl ; CHECK: movsbl
; CHECK: cmpl ; CHECK: cmpl
; CHECK: lock ; CHECK: lock cmpxchgb
; CHECK-NEXT: cmpxchgb
; CHECK: jne [[LABEL1]] ; CHECK: jne [[LABEL1]]
%2 = atomicrmw min i8* @sc8, i8 6 acquire %2 = atomicrmw min i8* @sc8, i8 6 acquire
; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]:
; CHECK: movsbl ; CHECK: movsbl
; CHECK: cmpl ; CHECK: cmpl
; CHECK: lock ; CHECK: lock cmpxchgb
; CHECK-NEXT: cmpxchgb
; CHECK: jne [[LABEL3]] ; CHECK: jne [[LABEL3]]
%3 = atomicrmw umax i8* @sc8, i8 7 acquire %3 = atomicrmw umax i8* @sc8, i8 7 acquire
; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]:
; CHECK: movzbl ; CHECK: movzbl
; CHECK: cmpl ; CHECK: cmpl
; CHECK: lock ; CHECK: lock cmpxchgb
; CHECK-NEXT: cmpxchgb
; CHECK: jne [[LABEL5]] ; CHECK: jne [[LABEL5]]
%4 = atomicrmw umin i8* @sc8, i8 8 acquire %4 = atomicrmw umin i8* @sc8, i8 8 acquire
; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]: ; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]:
; CHECK: movzbl ; CHECK: movzbl
; CHECK: cmpl ; CHECK: cmpl
; CHECK: lock ; CHECK: lock cmpxchgb
; CHECK-NEXT: cmpxchgb
; CHECK: jne [[LABEL7]] ; CHECK: jne [[LABEL7]]
ret void ret void
} }