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Improvement to the previous fix: branch following a delay slot of

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another delayed instr. would cause the later sanity-check (assertion)
in PhyRegAlloc.cpp to fail, even though there is really no error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7848 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2003-08-14 20:45:56 +00:00
parent 2925592230
commit 891bd82e79
2 changed files with 10 additions and 6 deletions
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8
lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp
View File

@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
MachineInstr* DelaySlotMI = *fwdMII;
set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
if (i+1 == DS)
set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
if (i+1 == DS)
set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
}
}
}

8
lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
View File

@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
MachineInstr* DelaySlotMI = *fwdMII;
set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
if (i+1 == DS)
set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
if (i+1 == DS)
set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
}
}
}