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Improvement to the previous fix: branch following a delay slot of
another delayed instr. would cause the later sanity-check (assertion) in PhyRegAlloc.cpp to fail, even though there is really no error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7848 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
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for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
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for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
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assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
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assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
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MachineInstr* DelaySlotMI = *fwdMII;
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MachineInstr* DelaySlotMI = *fwdMII;
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set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
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if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
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if (i+1 == DS)
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set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
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set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
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if (i+1 == DS)
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set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
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}
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}
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}
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}
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}
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@ -290,9 +290,11 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
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for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
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for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
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assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
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assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
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MachineInstr* DelaySlotMI = *fwdMII;
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MachineInstr* DelaySlotMI = *fwdMII;
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set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
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if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
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if (i+1 == DS)
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set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
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set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
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if (i+1 == DS)
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set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
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}
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}
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}
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}
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}
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