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Rename CreateReg to CreateRegs, and MakeReg to CreateReg.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107451 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-07-02 00:10:16 +00:00
parent f12ad66741
commit 89496d0eb7
5 changed files with 15 additions and 14 deletions
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2
lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -1211,7 +1211,7 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
// by bailing out early, we may leave behind some dead instructions,
// since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
// own moves. Second, this check is necessary becuase FastISel doesn't
// use CreateReg to create registers, so it always creates
// use CreateRegs to create registers, so it always creates
// exactly one register for each non-void instruction.
EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {

9
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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@ -172,18 +172,19 @@ void FunctionLoweringInfo::clear() {
ArgDbgValues.clear();
}
unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
/// CreateReg - Allocate the appropriate number of virtual registers of
/// CreateRegs - Allocate the appropriate number of virtual registers of
/// the correctly promoted or expanded types. Assign these registers
/// consecutive vreg numbers and return the first assigned number.
///
/// In the case that the given value has struct or array type, this function
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
unsigned FunctionLoweringInfo::CreateRegs(const Type *Ty) {
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, Ty, ValueVTs);
@ -194,7 +195,7 @@ unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = MakeReg(RegisterVT);
unsigned R = CreateReg(RegisterVT);
if (!FirstReg) FirstReg = R;
}
}

8
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
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@ -113,20 +113,20 @@ public:
/// different function.
void clear();
unsigned MakeReg(EVT VT);
/// isExportedInst - Return true if the specified value is an instruction
/// exported from its block.
bool isExportedInst(const Value *V) {
return ValueMap.count(V);
}
unsigned CreateReg(const Type *Ty);
unsigned CreateReg(EVT VT);
unsigned CreateRegs(const Type *Ty);
unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!");
return R = CreateReg(V->getType());
return R = CreateRegs(V->getType());
}
};

8
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -1508,7 +1508,7 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
// therefore require extension or truncating.
SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
JumpTableReg, SwitchOp);
JT.Reg = JumpTableReg;
@ -1559,7 +1559,7 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
TLI.getPointerTy());
B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
B.Reg, ShiftOp);
@ -6164,7 +6164,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
unsigned &RegOut = ConstantsOut[C];
if (RegOut == 0) {
RegOut = FuncInfo.CreateReg(C->getType());
RegOut = FuncInfo.CreateRegs(C->getType());
CopyValueToVirtualRegister(C, RegOut);
}
Reg = RegOut;
@ -6177,7 +6177,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
assert(isa<AllocaInst>(PHIOp) &&
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??");
Reg = FuncInfo.CreateReg(PHIOp->getType());
Reg = FuncInfo.CreateRegs(PHIOp->getType());
CopyValueToVirtualRegister(PHIOp, Reg);
}
}

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -732,7 +732,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
unsigned &R = FuncInfo->ValueMap[BI];
if (!R)
R = FuncInfo->CreateReg(BI->getType());
R = FuncInfo->CreateRegs(BI->getType());
}
bool HadTailCall = false;