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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
[DAGCombiner] Improve the folding of target independet shuffles to Undef.
When combining a pair of shuffle nodes, check if the combined shuffle mask is trivially Undef. In case, immediately fold that pair of shuffles to Undef. The lack of checks for undef masks was the root-cause of a poor-codegen bug in the dag combiner. Example: %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 1, i32 6> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 6> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 3> Before this patch, on x86 (with -mcpu=corei7) we failed to fold the entire sequence to Undef value and therefore we generated: shufps $-123, %xmm1, $xmm0 pshufd $-46, %xmm0, %xmm0 With this patch, the entire shuffle sequence is folded to Undef and no shuffles are generated in the output assembly. Added new test cases to test 'combine-vec-shuffle-5.ll'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
5dc48ac04a
commit
89cea3c36b
@ -10787,6 +10787,14 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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Idx = OtherSV->getMaskElt(Idx);
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Mask.push_back(Idx);
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}
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// Check if all indices in Mask are Undef. In case, propagate Undef.
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bool isUndefMask = true;
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for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
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isUndefMask &= Mask[i] < 0;
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if (isUndefMask)
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return DAG.getUNDEF(VT);
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bool CommuteOperands = false;
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if (N0.getOperand(1).getOpcode() != ISD::UNDEF) {
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@ -10932,6 +10940,14 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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Mask.push_back(Idx);
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}
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// Check if all indices in Mask are Undef. In case, propagate Undef.
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bool isUndefMask = true;
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for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
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isUndefMask &= Mask[i] < 0;
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if (isUndefMask)
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return DAG.getUNDEF(VT);
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// Avoid introducing shuffles with illegal mask.
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if (TLI.isShuffleMaskLegal(Mask, VT)) {
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if (IsSV1Undef)
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@ -255,3 +255,194 @@ define <4 x i8> @test4c(<4 x i8>* %a, <4 x i8>* %b) {
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; CHECK: blendps $13
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; CHECK: ret
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; Verify that the dag combiner correctly folds the following shuffle pairs to Undef.
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define <4 x i32> @test1b(<4 x i32> %A) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 5, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test1b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test2b(<4 x i32> %A) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 1, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 6, i32 7>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test2b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test3b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test3b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test4b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 4, i32 1, i32 1, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %B, <4 x i32> <i32 0, i32 3, i32 3, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test4b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test5b(<4 x i32> %A) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 5, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test5b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test6b(<4 x i32> %A) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 1, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 6, i32 7>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test6b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test7b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 6>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test7b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test8b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 1, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 6>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 3>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test8b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test9b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 2, i32 1>
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%3 = shufflevector <4 x i32> %2, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 1, i32 2>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test9b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test10b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 undef, i32 undef, i32 1, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %A, <4 x i32> <i32 0, i32 6, i32 1, i32 0>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 2>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test10b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test11b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 6>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test11b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <4 x i32> @test12b(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
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%2 = shufflevector <4 x i32> %1, <4 x i32> %B, <4 x i32> <i32 0, i32 3, i32 3, i32 0>
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%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 5, i32 1, i32 4>
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ret <4 x i32> %3
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}
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; CHECK-LABEL: test12b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <8 x i32> @test13b(<8 x i32> %A, <8 x i32> %B) {
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%1 = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 0, i32 undef, i32 1, i32 undef>
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%2 = shufflevector <8 x i32> %1, <8 x i32> %B, <8 x i32> <i32 1, i32 3, i32 1, i32 3, i32 1, i32 3, i32 1, i32 3>
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%3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> <i32 0, i32 9, i32 1, i32 10, i32 0, i32 9, i32 1, i32 10>
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test13b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <8 x i32> @test14b(<8 x i32> %A, <8 x i32> %B) {
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%1 = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 undef, i32 1, i32 1, i32 undef>
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%2 = shufflevector <8 x i32> %1, <8 x i32> %B, <8 x i32> <i32 0, i32 3, i32 3, i32 0, i32 0, i32 3, i32 3, i32 0>
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%3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> <i32 1, i32 9, i32 1, i32 8, i32 1, i32 9, i32 1, i32 8>
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test14b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <8 x i32> @test15b(<8 x i32> %A, <8 x i32> %B) {
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%1 = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 0, i32 1, i32 undef, i32 11, i32 0, i32 1, i32 undef, i32 11>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 8, i32 9, i32 2, i32 11, i32 8, i32 9, i32 2, i32 11>
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%3 = shufflevector <8 x i32> %2, <8 x i32> %A, <8 x i32> <i32 2, i32 2, i32 undef, i32 2, i32 2, i32 2, i32 undef, i32 2>
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test15b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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define <8 x i32> @test16b(<8 x i32> %A, <8 x i32> %B) {
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%1 = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 undef, i32 undef, i32 1, i32 10, i32 undef, i32 undef, i32 1, i32 10>
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%2 = shufflevector <8 x i32> %1, <8 x i32> %A, <8 x i32> <i32 0, i32 10, i32 2, i32 11, i32 0, i32 10, i32 2, i32 11>
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%3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> <i32 4, i32 9, i32 undef, i32 0, i32 4, i32 9, i32 undef, i32 0>
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ret <8 x i32> %3
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}
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; CHECK-LABEL: test16b
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; CHECK-NOT: blendps
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; CHECK-NOT: pshufd
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; CHECK-NOT: movhlps
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; CHECK: ret
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