6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-09 10:31:14 +00:00
Code Issues Projects Releases Wiki Activity

X86ISD::VZEXT_LOAD should produce and fold a chain.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-09-24 23:26:36 +00:00
parent 8e3455ba17
commit 8a186ae4aa
1 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6812,7 +6812,11 @@ static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
return SDValue();
return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
return ResNode;
}
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.