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Merge 98561 from mainline.
Avoid sibcall optimization if either caller or callee is using sret semantics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_27@99290 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1477,7 +1477,6 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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MachineFunction &MF = DAG.getMachineFunction();
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X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
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@@ -1779,7 +1778,8 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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if (isTailCall) {
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// Check if it's really possible to do a tail call.
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
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isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
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isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
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Outs, Ins, DAG);
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// Sibcalls are automatically detected tailcalls which do not require
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@@ -2297,6 +2297,8 @@ bool
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X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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bool isVarArg,
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bool isCalleeStructRet,
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bool isCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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@@ -2316,10 +2318,15 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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// Look for obvious safe cases to perform tail call optimization that does not
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// requite ABI changes. This is what gcc calls sibcall.
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// Do not tail call optimize vararg calls for now.
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// Do not sibcall optimize vararg calls for now.
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if (isVarArg)
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return false;
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// Also avoid sibcall optimization if either caller or callee uses struct
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// return semantics.
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if (isCalleeStructRet || isCallerStructRet)
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return false;
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// If the callee takes no arguments then go on to check the results of the
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// call.
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if (!Outs.empty()) {
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@@ -637,6 +637,8 @@ namespace llvm {
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bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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bool isVarArg,
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bool isCalleeStructRet,
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bool isCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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